Lsi Corporation

Seagate Technology Incorporated

Avago Technologies General IP (singapore) Pte. Ltd.

Broadcom International Pte. Ltd.

Jun Xiao

Fan Zhang

Shu Li

Haitao Xia

Shaohua Yang

Ming Jin

Lu Lu

Kaitlyn T Nguyen

Erich Franz Haratsch

George Mathew

Wu Chang

Xiufeng Song

Jianzhong Huang

Rui Cao

Bruce Alexander Wilson

Yu Liao

Jongseung Park

Ivana Djurdjevic

Jefferson E Singleton

Eric F Haratsch

The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that is operable to receive soft information corresponding to information accessed from a block of memory cells, and modify the soft information based upon a variance of the soft information and a median of the soft information to create corrected soft information, the corrected soft information being used to mitigate inter-cell interference in the block of memory cells.

Systems and methods for inter-cell interference mitigation in a flash memory

Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location.

Systems and methods for enhanced data recovery in a solid state memory system

Systems and methods for resource allocation for a large sector format processing may include, but are not limited to, operations for: determining non-convergence of a magnetic disc sub-sector of a first magnetic disc sector within a processing time frame allocated to the magnetic disc sub-sector; determining a convergence of a second magnetic disc sector occurring in less time than a processing time frame allocated to the second magnetic disc sector; and processing the magnetic disc sub-sector during a portion of the processing time frame allocated to the second magnetic disc sector remaining after processing of the second magnetic disc sector.

Online iteration resource allocation for large sector format drive

Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. In one particular example, a method is disclosed that includes: querying an input data set for an actual sync mark; forcing a proxy sync mark where the actual sync mark is not found in the input data set; applying data processing to the input data set to yield a processed output; correlating a potion of the processed output with a corresponding portion of the input data set to yield a true sync location; calculating a difference between the true sync location and the location of the forced sync mark to yield an offset; re-forcing the proxy sync mark based upon the offset; and re-applying the data processing to the input data set aligned using the re-forced proxy sync mark to yield a re-processed output.

Systems and methods for lost synchronization data set reprocessing

Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for quality based scheduling processing of data sets. In some cases, a priority indication associated with a data set is modified based upon one or more factors. As an example, the priority indication may be modified based upon a number of times that a given data set processed through both a data detector circuit and a data decoder circuit.

Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for use of a detector output by a data decoder. As an example, a data processing system is discussed that includes a data detector circuit operable to provide a first detector output and a second detector output, and a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output. The combined detector output includes a unified data set element generated by combining an element of the first input with a corresponding element of the second input.

Systems and methods for data processing using global iteration result reuse

The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods include receiving soft information corresponding to a series of voltage levels accessed from a block of flash memory cells, calculating corrected soft information based upon the received soft information and a variance of the soft information, and applying a data decoding algorithm to the corrected soft information to yield a data output.

Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. Some embodiments include one or both of a multi-algorithm data encoder circuit and/or a multi-algorithm data decoder circuit. In some cases, a first algorithm encoding is applied on a first section by section basis to a user data set yield an encoded portion; and a second algorithm encoding is applied on a second section by section basis to a data set derived from a subset of the encoded portion.

Systems and methods for multi-algorithm concatenation encoding and decoding

Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, estimating a voltage associated with the data in the data set corresponding to the critical location, calculating soft information corresponding to the critical location based at least in part on the estimated voltage, and re-applying the data decoding algorithm to the data set guided by the soft information to yield an updated decoded output.

Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. As one example, a data processing system is disclosed that includes a data detector circuit, a data decoder circuit, a memory circuit, and a scheduling circuit. The scheduling circuit is operable to select one of a first data set and the second data set as a detector input for processing by the data detector circuit.

Systems and methods for modified quality based priority scheduling during iterative data processing

Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.

Systems and methods for multi-dimensional data processor operational marginalization

Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. In one case, a system is disclosed that includes: a data transfer preparation circuit, a transfer characteristic determination circuit, and a a format insertion circuit. The data transfer preparation circuit is operable to receive a user data set and to generate an output data set based upon the user data set; the transfer characteristic determination circuit is operable to determine a distance between a first servo data wedge on a storage medium and a second servo data wedge on the storage medium; and the format insertion circuit is operable to dynamically augment the output data set with formatting information at a location selected based at least in part on the distance between the first servo data wedge and the second servo data wedge.

Systems and methods for large sector dynamic format insertion

Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

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Fremont, CA, United States of America

Jun Xiao