Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Jun Woo Myung

Akihisa Kuroyanagi

Yeong A Kim

Eun Sil Kim

Sung Min Song

Jae Kul Lee

Jin Su Kim

Young Ki Lee

Young Gwan Ko

Dae Hee Lee

Sun Woo Yun

Seon Ho Lee

Eun Seok Kim

Ha Kyeong Lee

Hyun Mi Kang

Tae-Ho Ko

A semiconductor package including a first redistribution structure including a first redistribution layer disposed therein, a first semiconductor chip disposed on the first redistribution structure, an insulating layer surrounding a sidewall of the first semiconductor chip, the insulating layer spaced apart from the first semiconductor chip in a horizontal direction, a first connection structure extending through the insulating layer in a vertical direction, connected to the first redistribution structure, and includes a first via disposed inside the insulating layer. A second connection structure disposed between the first semiconductor chip and the first connection structure, extends through the insulating layer in the vertical direction, connected to the first redistribution structure, and includes a second via disposed inside the insulating layer. A molding layer covering the first semiconductor chip, a sidewall and an upper surface of the insulating layer. At least a portion of the molding layer disposed between the first and second vias.

Semiconductor package and method for manufacturing the same

A semiconductor package includes: a first redistribution layer; a first semiconductor chip including a first side and a second side, wherein the first side faces the first redistribution layer; a first sealing material covering the second side of the first semiconductor chip and having a first filler content; a second sealing material formed on the first sealing material and having a second filler content lower than the first filler content; and a second redistribution layer disposed on the second sealing material.

Semiconductor package and fabricating method thereof

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.

Fan-out semiconductor package

A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, and having the active surface disposed on the connection structure to face the connection structure, and an encapsulant covering at least a portion of the semiconductor chip, wherein the semiconductor chip includes a groove formed in the active surface, and the groove has a shape in which a width of a region of at least a portion of an internal region located closer to a central portion of the semiconductor chip than the active surface is greater than a width of an entrance region.

Semiconductor package

A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed on side surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.

Semiconductor package including organic interposer

A semiconductor package includes a connection structure, a semiconductor chip, and an encapsulant. The connection structure includes an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer. The semiconductor chip has an active surface on which connection pads are disposed and an inactive surface opposing the active surface, and the active surface is disposed on the connection structure to face the connection structure. The encapsulant covers at least a portion of the semiconductor chip. The semiconductor chip includes a groove formed in the active surface and a dam structure disposed around the groove in the active surface.

An electronic component package includes a core member including an insulating layer, and having a first through-hole passing through the insulating layer, a semiconductor chip disposed in the first through-hole, and having an active surface on which a connection pad is disposed, and an inactive surface opposing the active surface, an encapsulant encapsulating the core member and the semiconductor chip, and filling at least a portion of the first through-hole, a connection member disposed on the core member and the semiconductor chip, and including a redistribution layer electrically connected to the connection pad, a backside metal layer disposed on the encapsulant, and covering at least the inactive surface of the semiconductor chip, and a backside metal via passing through the encapsulant, and connecting the backside metal layer to one side of the insulating layer. The backside metal via is in contact with the one side of the insulating layer.

Electronic component package with electromagnetic wave shielding

A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.

A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.

Fan-out semiconductor package module

Disclosed herein is a power module package including a heat radiating plate including a step difference portion around an edge portion thereof, a semiconductor chip mounted on a mounting surface of the heat radiating plate, an external connection terminal disposed on an outer periphery of the heat radiating plate, electrically connected to the semiconductor chip, and protruding outwards, a wire for electrical connection between the semiconductor chip and the external connection terminal; and a molding portion for encapsulation of the semiconductor chip and a portion of the heat radiating plate, and in particular, the molding portion does not intrude over an exposed surface of the lower portion of the heat radiating plate through the step difference portion. In addition, disclosed herein is a fabricating method for preventing flush of the molding portion on the exposed surface.

Power module package and method of fabricating the same

A semiconductor package includes a substrate, at least one electronic device, a lead frame, and a molded portion. The substrate has at least one indented portion formed as a groove therein. The electronic device is mounted on one surface of the substrate. The lead frame is bonded to the substrate and electrically connected to the electronic device. The molded portion seals the lead frame and the electronic device and includes at least one through hole extending the indented portion.

Semiconductor package with an indented portion and manufacturing method thereof

The semiconductor package according to an exemplary embodiment in the present disclosure includes: at least one electronic device; a lead frame including a plurality of leads electrically connected to the electronic device; a lead connecting member coupled to at least one of the leads; and a molded portion sealing the electronic device and the lead connecting member.

Growing community of inventors

Suwon-si, South Korea

Jun Woo Myung