National Semiconductor Corporation

Jun Wan

Peter R Holloway

Eric David Blom

Stuart H Urie

Gary E Sheehan

A semi-passive radio frequency identification (RFID) tag being coupled to a battery providing a battery voltage for powering a part of the circuitry of the RFID tag includes an RF communication block receiving and transmitting RF signals, a sensor block including a frequency ratio digitizing temperature sensor for alternately measuring the ambient temperature and the battery voltage, and a control logic block in communication with the RF communication block and the sensor block. The control logic controls the operation of the RF communication block and the sensor block and stores temperature and voltage measurement data generated by the sensor block. In one embodiment, the control logic block of the RFID tag operates based on a system clock and the sensor block provides a reference clock to the control logic block for use in calibrating the system clock of the control logic block.

RFID temperature logger incorporating a frequency ratio digitizing temperature sensor

A current source for generating a PTAT current using two bipolar transistors with an 1:A emitter area ratio implements a split resistor architecture to cancel mismatch errors in the current mirror of the current source. In one embodiment, a first resistor is coupled to the unit area bipolar transistor and a second resistor is coupled to the A-ratio-area bipolar transistor. The first resistor has a resistance value indicative of the emitter resistance rof the bipolar transistors while the second resistor has a resistance value satisfying the equation r*(lnA&#x2212;1). In another embodiment, an emitter area trim scheme is applied in a PTAT current source to cancel, in one trim operation, both bipolar transistor area mismatch error and sheet resistance variations. The emitter area trim scheme operates to modify the emitter area of the A-ratio-area bipolar transistor to select the best effective emitter area that provides the most accurate PTAT current.

Emitter area trim scheme for a PTAT current source

A buffer circuit () including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M, M) as the input device and a source follower, a second MOS transistor (M, M) as a transconductance amplifier device, and a third MOS transistor (M, M) as a folded cascode device. The first half circuit receives a buffer input voltage as the input voltage and the second half circuit receives a reference voltage as the input voltage. The first and second half circuits providing a pair of differential output signals indicative of the buffer input voltage. The buffer circuit has a very low input capacitance where the input capacitance does not vary with the buffer input voltage and other operating conditions, such as fabrication process, temperature and power supply voltage variations.

Low current offset integrator with signal independent low input capacitance buffer circuit

A method for charge balancing in a current input ADC including maintaining a low capacitance value at the integrator output node where the capacitance value is independent of the integrator output voltage and operating conditions, generating a first voltage pedestal at a first active device switch at the end of the autozero phase having a first voltage polarity and a first magnitude, generating a second voltage pedestal at a second active device switch at the end of the integration phase having an opposite voltage polarity and the first magnitude, and summing the first voltage pedestal with the second voltage pedestal. The difference between the first voltage pedestal and the second voltage pedestal results in a net voltage error. The first and second voltage pedestals have the first magnitude under all operating conditions of the modulator and the two voltage pedestals cancel to yield a small net voltage error.

Charge balancing method in a current input ADC

A frequency ratio digitizing temperature sensor for generating a linearity-corrected temperature output signal includes an input generation circuit receiving a PTAT current and a CTAT current and a frequency ratio ADC including data and reference oscillators. The input generation circuit generates a first current from the weighted sum of the PTAT current and the CTAT current and also generates a first corrected current being the sum of the first current and a first portion of the PTAT current. The input generation circuit provides a first output current indicative of the PTAT current and a first output voltage generated by applying the first corrected current to a first resistor for use with the data oscillator and provides a second output current being the first corrected current and a second output voltage generated by applying the first current to a second resistor for use with the reference oscillator of the ADC.

Frequency ratio digitizing temperature sensor with linearity correction

Self-regulating process-error trimmable PTAT current source

A dual-channel instrumentation amplifier includes two channels of PMOS transistor differential pairs which are configured in a Y-connection and cross-coupled to two diode-connected NMOS transistors. Each input channel has a non-linear voltage-current characteristic. But when the differential currents cancel at the NMOS transistor diodes, both input channels have the same differential input voltage, regardless of any non-linearity. As thus configured, a high accuracy instrumentation amplifier which operates in current mode is realized with excellent DC matching and high common mode rejection ratio. In one embodiment, the dual-channel instrumentation amplifier is used as input stage for the linear comparator to enable the linear comparator to operate at a high rate of speed with excellent channel matching.

Dual-channel instrumentation amplifier

A clock generator circuit incorporates a sub-PTAT (proportional to absolute temperature) current source and a super-PTAT current source for generating bias currents for a voltage reference generator and charging currents for a voltage ramp generator. The clock generator circuit further includes a linear comparator coupled to receive one or more switching voltage reference signals and a voltage ramp signal and generate a switching output signal as the clock signal. The clock signal is coupled to a clock decoder to generate the desired clock signals having the desired phase. The functional blocks of the clock generator circuit of the present invention operate together to generate a highly frequency stable clock signal. In one embodiment, the linear comparator incorporates a dual-differential-input (dual-channel) instrumentation amplifier as the comparator input stage to generate clock signals having clock frequency errors that are minimized over process, temperature and power supply variations.

Clock generator circuit stabilized over temperature, process and power supply variations

A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. In one embodiment, the modulation system includes a switched excitation source for exciting the input sensor and generating an input voltage step in response, and an integrator including an input capacitor, an amplifier and an accumulation capacitor. The input capacitor AC couples the input voltage step to the integrator to form an input charge. A reference charge packet is generated in a data dependent manner and coupled to the integrator simultaneously with the input charge. The integrator integrates charge associated with the sum of the input charge and the reference charge, when applied. The modulation system generates an output data stream exhibiting a ones density proportional to the magnitude of the average input voltage step.

Correlated double sampling modulation system with reduced latency of reference to input

A super-PTAT current source receives a PTAT reference voltage as input. The PTAT reference voltage is combined with the gate-to-source voltage difference of two unequal-area input transistors and the combined voltage is imposed on a high negative temperature coefficient resistor to produce an output current that is super-PTAT. A current source supplies a bias current to the super-PTAT current source whereby excess current provided by the current source is consumed by closed loop adjustments. The super-PTAT current source generates a super-PTAT current having a constant slope, excellent stability and very good linearity. In one embodiment, the super-PTAT output current is mixed with a sub-PTAT current in a preselected ratio to generate output currents having exactly the desired temperature coefficient.

Super-PTAT current source

A power-on reset circuit for an integrated circuit includes a voltage threshold detector circuit for generating a first signal, a DC biasing start-up circuit providing start-up currents and a first control signal, a self-regulating watchdog current source providing bias currents and a counter circuit for counting a predetermined number of cycles when enabled by the first control signal and providing a second control signal when the count is completed. The POR circuit asserts the reset signal when the first signal is asserted and deasserts the reset signal when both the first signal and the second control signal are deasserted. The POR circuit merges accurate detection of the full range of Vdd events with a self-adapting current source. In addition, the POR circuit employs 'pulse-stretching' techniques operating independently but mutually working together to create a POR assertion persistence in the time domain that further enhances the reliability of POR signal effectiveness.

Power-on reset circuit with low standby current and self-adaptive reset pulse width

A self-regulating current source is formed by a PMOS current mirror and an interconnected pair of NMOS transistors. The NMOS transistors are sized differently and forced to operate at similar currents. The difference of the Vgs voltages of the NMOS transistors is impressed across the resistor to develop a stable output current. In particular, the current source starts reliably at low supply voltages and operates to reliably generate a stable low output current at a well-controlled operating point. The self-regulating current source can be used effectively as the watchdog current source of a power-on reset circuit to ensure reliable and robust operation even at low Vdd voltage values.

Self-regulating low current watchdog current source

A digitizing temperature measurement system for providing a digital temperature measurement includes an excitation source for providing switched excitation currents to two or three temperature sensing elements and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The system utilizes synchronous AC excitation of the temperature sensing elements and an AC coupled analog-to-digital converter input. The temperature measurement system also implements correlated double sampling for noise cancellation to provide low noise and highly accurate analog-to-digital conversions. The modulator receives a charge domain reference signal generated by a reference charge packet generator incorporating a charge based bandgap subsystem. Therefore, the temperature measurement system can be operated at very low supply voltages, such as 1.0 Vdc. A low noise and highly accurate temperature measurement system is thus realized where temperature measurements of very high resolutions (up to 16 bit) can be attained.

Digitizing temperature measurement system and method of operation

A circuit in an integrated circuit for measuring temperature dependent voltages of a temperature sensing element includes a voltage generator circuit providing the temperature dependent voltages, a first sampling switch and a second sampling switch. The voltage generator circuit includes a temperature sensing element being excited by a first switched current and a second switched current. The first and second sampling switches sample a first voltage and a second voltage at the temperature sensing element while the temperature sensing element is being excited by the second current and the first current, respectively. Each of the first and second sampling switches includes a boosted switch circuit incorporating a pedestal voltage compensation circuit. The sampled first and second voltages are coupled to be stored on capacitors external to the integrated circuit. The difference between the first voltage and the second voltage is measured to determine the temperature of the integrated circuit.

Synchronized delta-VBE measurement system

A digitizing ohmmeter system for providing a digital resistance measurement includes a current source for providing an excitation current to an impedance-varying input sensor and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The system utilizes synchronous AC excitation of the input sensor and an AC coupled analog-to-digital converter input. The digitizing ohmmeter system also implements correlated double sampling for noise cancellation to provide low noise and highly accurate analog-to-digital conversions. The ADC circuit includes a reference signal generator generating a resistance reference signal by time-sharing the excitation current with the input sensor. The digitizing ohmmeter system thereby realizes fully ratiometric operation such that neither a precise current source nor a precise voltage source is required for accurate resistance measurements.

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Wilmington, MA, United States of America

Jun Wan