Mitsubishi Electric Corporation

Jun Tomisawa

Kenichi Morokuma

Kazuyasu Nishikawa

Tetsuya Uchida

Akinori Nishizawa

Yusaku Ito

Shoichi Orita

Yusuke Nakamatsu

A semiconductor device improved in deterioration detection accuracy by using an inductance of a bonding wire. The semiconductor device includes a first conductor pattern formed on the insulating substrate, the main current of the semiconductor die device flowing through the first conductor pattern; a second conductor pattern formed on the insulating substrate for sensing the potential of the surface electrode of the semiconductor die device; a first bonding wire for connecting the surface electrode and the first conductor pattern; and a second bonding wire. Further, there is a voltage sensing unit which is connected to the first conductor pattern and the second conductor pattern to sense a potential difference between the first conductor pattern and the second conductor pattern at the time of switching of the semiconductor die device; and a deterioration detection unit for detecting deterioration of the first bonding wire by using the sensed potential difference.

Semiconductor device and power converter

Peeling in an electronic module is sensed. An electronic module according to the present invention includes a specified conductor, an insulating layer, a wiring layer, and a capacitance-to-voltage converter. The wiring layer includes a sense electrode. The capacitance-to-voltage converter is connected to the sense electrode. The sense electrode is opposed to a portion of the specified conductor via the insulating layer, and forms a capacitance with the portion. The capacitance-to-voltage converter is configured to output a voltage according to the capacitance.

Electronic module and power module

A programmable decoder () includes a counter (A) whose count value increases for each clock; an address decoder (A) for converting the count value into an address; a storage (A) storing a table defining data according to the address converted from the count value; and a latch unit () for latching the data according to the address output from the storage (A). A variable driver () includes a plurality of MOS transistors (), (), (). The latch unit (A) has outputs connected to control electrodes of a plurality of MOS transistors (), (), (). The table defines a plurality of data items in the table so that the driving force of the variable driver () increases with an increase of the count value. A counter (A) updates the count value while the arm control signal is being activated.

Gate driver and power module

A first circuit outputs transmission signals that change between 'H' and 'L' in a period of an oscillation signal in addition to a transition time of an input signal when it changes to &#x201c;H&#x201d; or &#x201c;L&#x201d;. Control protection elements invalidate induced voltage signals obtained from transformers for first and second mask periods in response to transmission signals. Buffer circuits and Schmitt circuits generate a first signal and a second signal, each indicating &#x201c;H&#x201d; for a relatively long period, on the basis of &#x201c;H&#x201d; of the induced voltage signals. A control circuit invalidates the first signal and the second signal when both the first signal and the second signal indicate &#x201c;H&#x201d;.

Signal transmission circuit and power conversion device

A signal transmission circuit includes, in each of a first circuit connected to a first coil of an insulating transformer and a second circuit connected to a second coil of the insulating transformer, a transmitting circuit, a receiving circuit, a coil-side switching circuit, an input/output-side switching circuit, an abnormality detection circuit, a delay circuit, and a direction control section. In the signal transmission circuit, the direction control section controls the switching circuit to switch a signal direction between input and output, and the switching circuit switches between transmission and reception. The delay circuit delays a received signal and returns the resultant signal to the transmitting side, and the abnormality detection circuit detects abnormality to perform self-diagnosis.

Signal transmission circuit and power conversion device equipped with same

A transmitter circuit feeds to a transmitter coil, every time transmission data changes in logical value, a current signal in pulse form having a positive or negative polarity that is alternately inverted in response to each change in logical value; and a receiver circuit inputs induction voltage signals each being double pulses having both positive and negative polarities, which have been induced in a receiver coil by the current signal fed to the transmitter coil, to demodulate the transmission data. The receiver circuit includes: an amplifier that amplifies the induction voltage signals of double pulses induced in the receiver coil; and a signal generating unit that, when detecting first single pulses in the induction voltage signals of double pulses amplified by the amplifier, sets up an insensitive period for second single pulses therein, to generate an output signal corresponding to the transmission data, based solely on the first single pulses.

Signal transmitting circuit

A signal transmission circuit includes an isolation circuit, first and second grounded gate circuits, first and second MOS transistors, and a comparator. The isolation circuit such as a thin-film transformer outputs complementary first and second output signals, based on an input signal. The first and second grounded gate circuits receive and amplify the first and second output signals, respectively. The first and second MOS transistors are connected between a power supply node and the first and second grounded gate circuits, respectively, for adjusting the first and second output signals. The comparator compares output from the first grounded gate circuit with output from the second grounded gate circuit.

Signal transmission circuit

A semiconductor integrated circuit includes a differential amplifier circuit receiving first and second input voltages, a latch circuit comparing a voltage received from a first output terminal of the differential amplifier circuit through a first capacitor and a voltage received from the second output terminal of the differential amplifier circuit through a second capacitor and providing a digital signal representing a result of a comparison between the first and second input voltages, and a third capacitor having a first terminal coupled to a second terminal of the first capacitor and a second terminal coupled to a second terminal of the second capacitor.

Growing community of inventors

Chiyoda-ku, Japan

Jun Tomisawa