Western Digital Technologies, Inc.

Cnex Labs, Inc.

Sandisk Technologies Inc.

Jun Tao

Niang-Chu Chen

Mark Joseph Dancho

Xiaoheng Chen

Chandan Mishra

Amir Hossein Gholamipour

Mark David Myran

Namhoon Yoo

Chih-Chieng Cheng

Shanying Luo

Scott Kayser

Bo Jiang

Apparatus, media, methods, and systems for data storage systems and methods for self-adaptive chip-enable setup time. A data storage system may comprise one or more non-volatile memory device and a controller. The controller is configured to determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, increase a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device.

Data storage systems and methods for self adaptive chip-enable setup time

Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.

Logical to physical mapping management using low-latency non-volatile memory

Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.

Data storage systems and methods for improved data relocation based on read-level voltages associated with error recovery

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

Dynamic multi-stage decoding

Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.

Adjustable read retry order based on decoding success trend

Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

A storage system includes: a control processor, configured to: read user data with a read threshold, determine which threshold adjustment range has been activated by reading a 1 and 0 counter, select an adjusted read threshold, based on the threshold adjustment range, to reread the user data in a physical block using the adjusted read threshold to correct the user data; and reading the user data in the physical block using the adjusted read threshold selected from the threshold adjustment range.

Storage system with predictive adjustment mechanism and method of operation thereof

A storage system includes: a control processor, configured to: read user data with a read threshold, detect an uncorrectable error in the user data, detect a sector balanced when the number of 1's and 0's in the user data is within the difference stored in a range register, apply an XOR RAID recovery to correct the uncorrectable error in the user data; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured to forego an additional read of a sector N with a different value of the read threshold when the sector balanced initiates the XOR RAID recovery.

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Ladera Ranch, CA, United States of America

Jun Tao