Shanghai Huali Microelectronics Corporation

Shanghai Huali Integrated Circuit Corporation

International Business Machines Corporation

Saint-gobain Glass France

Saint-gobain Sekurit France

Jun Tan

Jun Ma

Qiang Yan

Qiuming Huang

HaiFeng Zhou

Michael Labrot

Xiaofeng Guo

Juliette Jamart

Jia Niu

Jian Zhong

Hong Wei Dai

Gong Qiong Li

Jianqin Gao

Jiaqi Hong

Florian Flamary-Mespoulie

An exterior trimming part for a pillar of a vehicle, includes a bracket fixedly connected to the pillar, and a glass cover plate fixedly connected to the bracket and covering an exterior surface of the bracket. The bracket has a receiving space opened at least towards the glass cover plate. The exterior trimming part further includes an electronic component disposed at the receiving space. The exterior trimming part not only has good scratch resistance, but also has intelligent functions.

Exterior trimming part for pillar of vehicle

The present application discloses an epitaxial growth method for an FDSOI hybrid region, comprising: step, providing an FDSOI substrate structure; step, forming a trench; step, performing first isotropic epitaxial growth, wherein a top surface of a first semiconductor epitaxial sublayer is located in a plane between a top surface and a bottom surface of a dielectric buried layer, and a second semiconductor epitaxial sublayer comprise a lateral protruding structure on the side face of the semiconductor top layer; and step, performing second epitaxial growth having a growth rate of the first crystalline face, which is greater than a growth rate of the second crystalline face, wherein the third semiconductor epitaxial sublayer has a chamfered recess near the side face of the semiconductor top layer, finally the lateral protruding structure is located in the chamfered recess.

Epitaxial growth method for FDSOI hybrid region

A manufacturing method of a fin semiconductor device comprises: providing a substrate, wherein a fin channel base is patterned on and in contact with the substrate; epitaxially growing a top part of the fin channel base and extending the top part of the fin channel base sideways and upward to form a fin channel core; oxidizing the fin channel base to form a fin channel structure, wherein the fin channel structure comprises the fin channel core surrounded with an oxide layer at the top part of the fin channel base and an intermediate part of the fin channel base under the top part; and removing the oxide layer to expose the fin channel core, wherein the fin channel core suspends over the substrate.

Fin semiconductor device and method for making the same

A manufacturing method of a fin semiconductor device is disclosed. The method includes: providing a substrate; etching the substrate the first time to form a fin channel structure which protrudes from the substrate; forming a protective oxide layer on two sidewalls and the top surface of the fin channel structure; etching a the second time to form the base part of the fin channel structure, wherein the base part is not covered by the protective layer; oxidizing the base part of the fin channel, when the upper part of the fin channel is blocked from oxidation by the protective layer; removing both the protective layer and the oxidized base part of the fin channel structure, so that the upper part of the fin channel structure is suspended over the substrate.

The present disclosure discloses a semiconductor device, which comprises: an embedded gate structure with a bottom embedded in a semiconductor substrate; a channel region formed below the bottom surface of the embedded gate structure; a source region and a drain region formed on the two sides of the embedded gate structure; an embedded epitaxial layer formed in the source region or the drain region, the bottom surface of the embedded gate structure being in flush with the maximum stress position of the embedded epitaxial layer. The present disclosure further discloses a method for manufacturing a semiconductor device. The present disclosure can enable the channel region to be located in the maximum stress region of the embedded epitaxial layer, thereby improving the mobility of channel carriers to the utmost extent and improving the conduction current of the device.

Semiconductor device and method for manufacturing the same

A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.

SiGe source/drain structure

Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.

Embedded SiGe epitaxy test pad

SiGe source/drain structure and preparation method thereof

A method of fabricating a semiconductor device is disclosed. The method includes the steps of forming recesses in a semiconductor substrate; epitaxial growing a first SiGe seed layer with constant Ge content in the recesses; epitaxial growing a second SiGe layer with a constant Ge content higher than the Ge content of first SiGe seed layer on the first SiGe seed layer; epitaxial growing a third SiGe layer with a constant Ge content lower than the Ge content of the second SiGe layer; and forming a cap layer on the third SiGe layer.

Method of fabricating semiconductor device and semiconductor device fabricated thereby

The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor device that comprises a diamond-shaped cavity, and the shaped cavity is filled with silicon and germanium material. There are other embodiments as well.

Shaped cavity for SiGe filling material

The invention discloses a treatment process for a semiconductor, comprising providing a substrate; defining a trench opening region of the substrate; performing plasma etching to form a trench region at the trench opening region; subjecting the substrate to a first epitaxial process with a first plurality of gaseous species to form a protective layer overlaying at least the first sidewall and the bottom of the trench region; and subjecting the substrate and the protective layer to a second epitaxial process with a second plurality of gaseous species to form a filling material overlaying the protective layer and being positioned at least partially within the trench region. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, at least one epitaxial process to form the protective layer overlaying at least the first sidewall and the bottom of the trench region corresponds to form a filling material overlaying the protective layer and being positioned at least partially within the trench region.

Methods and systems for using conformal filling layers to improve device surface uniformity

The present invention relates to a method and an apparatus for estimating a clock skew. The method comprises: obtaining a basic clock skew of each clock tree in the circuit; judging whether two units are in a same clock domain; if they are in different clock domains, estimating the clock skew between units to be a larger one of basic clock skews of the clock trees corresponding to these two unit; if these two units are in the same clock domain, further judging whether they are in a same hierarchical logic block; if they are in different hierarchical logic blocks, estimating the clock skew between units to be the basic clock skew of the clock tree of these two units plus additional clock skew caused by different hierarchical logic blocks. The apparatus is corresponding to the method. With the method and apparatus, the clock skew in the circuit can be estimated more accurately, which improves the efficiency of circuit design.

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Shanghai, China

Jun Tan