Kabushiki Kaisha Toshiba

Toshiba Infrastructure Systems & Solutions Corporation

Api Corporation

Toshiba Corporation

Ube Corporation

Jun Takehara

Hiroshi Nakatani

Motohiko Okabe

Yoshito Sameda

Akira Sawada

Hiroyuki Nishikawa

Makoto Toko

Masato Murai

Daiki Okado

Naruhiko Aramaki

Toshikazu Kawamura

Fumiyasu Miyoshi

Atsushi Inoue

Minoru Saito

Masayuki Murakami

Hiroyuki Maehara

Tomoko Maeda

Shinya Kono

Shigeki Katayama

Naoya Ohnishi

Tsugihiko Hidaka

Takashi Ohtani

Yuuji Umeda

Hiroyuki Kusakabe

Yukitaka Yoshida

Kouichi Takene

Yoichi Takayanagi

Wataru Yamamori

Takaya Shono

Yukihiko Maede

Yasutaka Umeda

The present invention aims to provide a method for producing a (2S,5R)-5-(protected oxyamino)-piperidine-2-carboxylic acid derivative at a low cost that can be performed under mild reaction conditions not requiring a facility at an extremely low temperature, is safer, can control the quality of the desired product with ease, and shows good workability in the site of production. A method for producing a compound represented by the formula (2): wherein PGis an amino-protecting group, PGis an amino-protecting group, PGis a hydroxyl-protecting group, LG is a leaving group, and R is a hydrocarbon group having 1-8 carbon atoms and optionally having substituent(s), including a step of reacting a compound represented by the formula (1): wherein each symbol is as defined above, with a hydroxylamine derivative represented by the formula PGNHOPGwherein each symbol is as defined above, in the presence of a base in a solvent.

Method for producing amino acid derivatives

A method for producing a compound represented by the formula (1): wherein LG is a leaving group, PGis an amino-protecting group, and R is a hydrocarbon group having 1-8 carbon atoms and optionally having substituent(s), comprising with an amino group protecting agent to obtain a compound represented by the formula (7): or a salt thereof; and

A charging system includes an electric bus and a charger. The charger includes a supply unit and a second communication unit. The supply unit supplies power to the electric bus stopped at a preset position. If power is being supplied to the electric bus by the supply unit, the second communication unit transmits a first identifier of the charger, if power is not being supplied to the electric bus by the supply unit, transmits a second identifier that is an identifier of the charger and different from the first identifier, and if a first command is received from the electric bus, transmits and receives information related to charging of a storage functional unit included in the electric bus, with the electric bus being a transmission source of the first command, using radio communication.

Charging system and charger

According to embodiments, an electric bus includes an electricity storage function unit, a power receiving unit, a charger, a driving unit, doors, and a controller. The controller transmits a first signal including information capable of identifying an attribute of the electric bus and instructing an external device to start charging the electricity storage function unit, to the external device, upon detecting at least one of the doors is opened; and transmits a second signal instructing the external device to stop charging the electricity storage function unit, to the external device, upon detecting all the doors are closed.

Electric bus and charging system

A microprocessor operation monitoring system whose own tasks are constituted by associating beforehand the task number of the task that is next to be started up, for each of the tasks constituting the program, and abnormality of microprocessor operation is detected by comparing and determining whether or not the announced task and the task to be started up match.

Microprocessor operation monitoring system

A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

Clock diagnosis circuit

A substation instrument control system is disclosed. The substation instrument control system includes a plurality of transformers that generate a plurality of waveform signals representing electric properties of a substation instrument main body. A merging unit is communicatively coupled to the plurality of transformers and includes a signal processing unit and a control unit. The signal processing unit receives the plurality of waveform signals from the plurality of transformers and converts the plurality of waveform signals to a digital signal. The control unit controls operation of the signal processing unit using a setting data. An intelligent electronic device is communicatively coupled to the merging unit and receives the digital signal from the merging unit.

Substation instrument control system

When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint () that receives a memory read request transmitted by the root complex, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex () returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.

PCI.Express communication system and communication method thereof

A first arithmetic operator () includes a first modular arithmetic coding encoder () for encoding a numeric data transmitted by a command from a central controller () into a modular arithmetic code, a first arithmetic operation processor () using the numeric data as modular arithmetic coded as an input operand, for executing an arithmetic operation based on a command from the central controller (), to provide an output in the form of a modular arithmetic code, and a first modular arithmetic code decoder () for determining presence or absence of a bit error in the numeric data output from the first arithmetic operation processor, correcting the bit error, if detected any, to output a decoded numeric data.

Industrial controller

A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line

For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator () has processor cores () connected to a boundary scan bus (), and adapted to mutually diagnose opponent processor cores for troubles, by boundary scan testing each other in a time-dividing manner.

Control apparatus

An object is to provide a redundant supervisory control system and a redundancy switching method thereof. In the redundant supervisory control system, remote I/O apparatuses are less likely to be inaccessible, even in a case where failures occur in plural locations. Thus, the reliability of the system is enhanced. The redundant supervisory control system including a plurality of first loop interface units in each of a pair of controllers, second loop interface units, and communication cables each connecting the plurality of first and second loop interface units with one another in a circular loop. The redundant supervisory control system is configured by connecting the controllers and the remote I/O units to one another in a plurality of loop networks. In a case where abnormality in the loop networks is detected by use of received data in the networks, the first and second loop interface units that can perform normal reception are automatically selected.

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Tokyo, Japan

Jun Takehara