Mitsubishi Denki Kabushiki Kaisha

Jun Takasoh

Kimio Ueda

A half-rate clock and data recovery (CDR) circuit includes a half-rate phase detector for detecting phases of an input signal and a half-rate clock, a charge pump circuit, a low-pass filter and a voltage controlled oscillator for feeding the half-rate clock back to the half-rate phase detector. The half-rate phase detector includes a one-pulse delay circuit for generating a delay of one pulse . The phase comparison polarity of the half-rate phase detector including the one-pulse delay circuit enables use of an N type LC voltage controlled oscillator as the voltage controlled oscillator.

Half-rate clock and data recovery circuit

A half-rate clock and data recovery circuit includes a phase detector capable of operating at a half-rate, a charge pump circuit, a low pass filter, and a voltage controlled oscillator. The phase detector includes a selector circuit which receives uninverted and inverted signals from respective latches of the phase detector and an uninverted and inverted half-rate clock and outputs uninverted and inverted retimed signals supplied to the charge pump so that the charge pump produces a full-rate output in response to a half-rate input. The circuit provides greater operating margin.

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Tokyo, Japan

Jun Takasoh