Skhynix Inc.

Sungkyunkwan University

Daegu Gyeongbuk Institute of Science and Technology

Jun Sun Hwang

Jin Ha Hwang

Kwan Su Shon

Kyeong Min Chae

Dae Ho Yang

Jin Young Kim

Min Su Kim

Jung Hwan Lee

Yo Han Jeong

Kwang Soon Kim

Tae Hee Han

Soon Sung An

Hong Soo Choi

Keun Seon Ahn

Sung Jun Lim

Jae Hoon Jung

Jae Hyeong Hong

Hyunki Lee

Beom Joo Kim

Hwajun Jeong

Su Han Lee

Disclosed is a guidewire steering micro-robot. The guidewire steering micro-robot includes a guidewire, and a steering unit provided at an end portion of the guidewire, the steering unit including a magnetic body to control and steer a position of the guidewire by an external magnetic field.

Guidewire steering micro-robot

A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

Duty cycle correction circuit and method of operating the same

The present technology relates to an electronic device. A storage device in which a memory device controls an ODT operation to improve operation performance of the memory device with a small number of pins includes a plurality of memory devices comprising a target memory device in which an operation is performed and non-target memory devices, and a memory controller configured to control the plurality of memory devices. Each of the plurality of memory devices includes an on die termination (ODT) flag generator configured to generate a flag that indicates that an ODT operation is possible for the non-target memory devices, and an ODT performer configured to determine whether the ODT operation is an ODT read operation for a read operation or an ODT write operation for a write operation based on the flag and configured to generate an enable signal that enables the ODT read operation or the ODT write operation.

Storage device and method of operating the same

A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.

Dividing circuit system and semiconductor memory system including thereof

The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.

Data transmission circuit for preventing a node from floating and method of operating the same

A semiconductor device includes a plurality of semiconductor chips vertically stacked and electrically coupled to one another through TSVs (Through-Silicon Vias), a plurality of semiconductor elements formed in each of the semiconductor chips, a plurality of nodes suitable for coupling the semiconductor elements to one another, and a node control device suitable for being provided in each of the nodes, deciding whether to couple the node to a communication path based on a temperature of the node, and setting a shortest communication path among the semiconductor elements.

Semiconductor device having network-on-chip structure and routing method thereof

Growing community of inventors

Gyeonggi-do, South Korea

Jun Sun Hwang