Samsung Electronics Co., Ltd.

Jun-soo Lee

Ji-Young Kim

Seung-Jun Lee

Sung-eui Kim

Jong-Bom Seo

Hoon Jeong

Young-Seung Cho

Chan-Won Kim

Jae-Hoon Kim

Jeon-Il Lee

Hong-Rae Kim

Kyung-hak Min

Naoyuki Kato

The inventive concept provides a method of manufacturing a semiconductor device using a plasma etching apparatus including an alignment chamber and a process chamber. The method includes: loading a wafer in the alignment chamber of the plasma etching apparatus; rotating the wafer loaded in the alignment chamber according to a plurality of heating zones arranged in an electrostatic chuck of the process chamber, thereby rotating a reference point of the wafer; transferring the wafer that was rotated in the alignment chamber onto the electrostatic chuck of the process chamber; and plasma-etching the wafer that was rotated in the alignment chamber on the electrostatic chuck of the process chamber.

Method of manufacturing semiconductor device by using plasma etching apparatus

Methods of forming patterns for semiconductor devices are provided. A method may include preparing a substrate including an etch target layer on a surface of the substrate; forming a mask pattern that includes a lower masking layer having a first density and an upper masking layer having a second density that is less than the first density, on the etch target layer; forming spacers that cover sidewalls of the lower masking layer and the upper masking layer; removing the mask pattern; and etching the etch target layer by using the spacers as an etching mask.

Methods of forming patterns with multiple layers for semiconductor devices

A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

Semiconductor devices including capacitors and methods of manufacturing the same

Semiconductor devices including capacitors

A bass enhancing apparatus and method for enhancing bass include generating harmonics of the bass when an input signal is reproduced using a miniaturized speaker. The bass enhancing method includes extracting a bass component of an input signal, generating harmonics of the extracted bass component, synthesizing the generated harmonic signals and the input signal, and outputting the synthesizing result to an output terminal. The generating of the harmonics includes compressing a dynamic range of an amplitude level of each harmonic component at a predetermined distribution ratio.

Bass enhancing apparatus and method

Growing community of inventors

Seoul, South Korea

Jun-soo Lee