Sungkyunkwan University

Jun Sin Yi

Chung Yuen Won

Sung Gon Jung

Mi Na Kim

Hoon Gi Lee

Bong Yeon Choi

Tae Gyu Kim

Chang Gyun An

Kyung Soo Jang

Byoung Deog Choi

Kwang Su Na

Kyoung Min Kang

Jae Hyun Cho

A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.

Method for controlling fault using switching technique of three phase four wire interlinking converter

Provided are nanocrystal silicon layer structures formed using a plasma deposition technique, methods of forming the same, nonvolatile memory devices including the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices. A method of forming a nanocrystal silicon layer structure includes forming a buffer layer on a substrate and forming a nanocrystal silicon layer on the buffer layer by a plasma deposition technique using silicon (Si)-containing gas and hydrogen (H)-containing gas. In this method, the nanocrystal silicon layer can be directly deposited on a glass substrate using plasma vapor deposition without performing a post-processing process so that the fabrication of a nonvolatile memory device can be simplified, thereby reducing fabrication cost.

Nanocrystal silicon layer structures formed using plasma deposition technique, methods of forming the same, nonvolatile memory devices having the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices

A thin film transistor (TFT), a method of forming the same and a flat panel display device having the same are disclosed. The TFT includes a buffer layer and a semiconductor layer which are sequentially disposed on a substrate, a gate pattern including an insulating pattern and a gate electrode pattern which are sequentially disposed on the semiconductor layer, source and drain regions defining a portion of the semiconductor layer below the gate pattern as a channel area, formed by doping the semiconductor layer disposed at both sides of the gate pattern with impurities, and extending from both sides of the channel area, a passivation layer which covers the entire surface of the substrate having the gate pattern, a first metal electrode which penetrates a portion of the passivation layer disposed on the source area and a portion of the source region below the portion of the passivation layer to be electrically connected with the source region, and a second metal electrode which penetrates a portion of the passivation layer disposed on the drain area and a portion of the drain region below the portion of the passivation layer to be electrically connected with the drain region. According to the present invention, a metal is infiltrated into source and drain regions to disperse an electric current when a TFT operates, and thus charge mobility is improved, and damage of a drain region caused by the excessive current density is prevented, leading to the long lifespan and excellent performance.

Thin film transistor, method of forming the same and flat panel display device having the same

Growing community of inventors

Gwacheon-si, South Korea

Jun Sin Yi