Samsung Electronics Co., Ltd.

Jun-sik Hwangbo

Jae-Yeong Do

Jae-young Do

Dae-sik Weon

A device for changing a frequency of an internal control clock for testing a chip, by incorporating a mode selection circuit (30) and a high voltage detection circuit (40) in a serial input/output memory. The mode selection circuit (30) is connected between two selected adjacent circuits C.sub.n-2, C.sub.n-1 among a plurality of frequency conversion circuits C.sub.1 . . . C.sub.n, for accessing selectively either a clock pulse CP.sub.n-2 from the frequency conversion circuit C.sub.n-2, arranged in front thereof or a system clock XSK, in dependence upon an internal voltage sense signal IV, IVB. The high voltage detection circuit (40) transmits the internal voltage sense signal to the mode selection circuit (30) by detecting a level of externally applied voltage XV. The internal control clock ICK provided by this device attains a period of T.sub.XSK .times.2.sup.n-M+1, wherein 'M' is a number of the counter receiving the mode selection signals MS, MSB next to the mode selection circuit.

Serial input/output memory with a high speed test device

In a nonvolatile semiconductor memory device having a plurality of word lines, bit lines, sense lines, nonvolatile semiconductor memory cells, column selecting transistors, a page buffer circuit, data lines, an input driver/sense amplifier, an input buffer an input/output register and a comparator, a secret access code is defined in such a manner that a first secret access code is latched in the page buffer circuit, a second secret access code inputted by the input buffer is compared with the first secret access code read by the input/output register by bytes in the comparator, and if the first and second access codes match, the first secret access code latched in the page buffer is written in the cells of the row line designated in advance among the nonvolatile memory cells.

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Seoul, South Korea

Jun-sik Hwangbo