Hynix Semiconductor Inc.

Skhynix Inc.

Jun Seop Chung

Joong Seob Yang

You Sung Kim

Jong Hyun Wang

Seok Jin Joo

Duck Ju Kim

Byung Ryul Kim

An Ho Choi

Tae Ho Shin

Tao Ho Shin

A data storage device includes a nonvolatile memory device including a buffer region and a main region; and a controller suitable for controlling a buffer write operation of the nonvolatile memory device such that write-requested first data is stored in the buffer region, and controlling a main write operation of the nonvolatile memory device such that the first data stored in the buffer region is stored in the main region according to a write mode, wherein the nonvolatile memory device performs the buffer write operation regardless of the write mode.

Data storage device and operating method thereof

According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache program signal is input, a determination is made as to whether a first program verify operation is being performed, and if so, the verify operation is stopped, the second data is input, and the first program verify operation is restarted.

Program method of nonvolatile memory device

A nonvolatile memory device includes a data conversion unit including an encoder and a decoder. The encoder sets data for each of word lines and creates second data to be programmed into a plurality of memory cells by performing a logical operation on the set data and first data input for programming. The decoder creates the first data by performing a logical operation on the second data that is read from the memory cells and the set data.

Nonvolatile memory device and method of operation to program/read data by encoding/decoding using actual data and random data for program/read operation

A non-volatile memory device is disclosed. The non-volatile memory device includes an encoder configured to set random data in a unit of a word line, and generate second data to be programmed in a memory cell by performing logic operation about the random data and first data inputted for program, and a data converting circuit configured to have a decoder for generating the first data by performing logic operation about the second data read from the memory cell and the random data.

Non-volatile memory device and method of operating the same

A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a N(N&#x2267;3, N is an integer) read command.

Read method of memory device

A page buffer circuit includes a bit line selection circuit, a main register, a program transmission circuit, a temporary register, and a verification transmission circuit. The verification transmission circuit transmits data stored in the temporary register to the main register through a sensing node in response to a transmission control signal during a program verification operation. A memory cell that has been determined to be programmed in a previous program verification process is verified again in a next program verification process.

Page buffer circuit of flash memory device and program operation method thereof

A method of operating a packaged flash memory module includes applying a first program or erase command and a first address associated with the first commend to a first flash memory chip of a plurality of flash memory chips that are arranged within the packaged flash memory module; applying a second program or erase command and a second address associated with the second commend to a second flash memory chip of the plurality of flash memory chips that are arranged within the packaged flash memory module, the second command being applied to the second flash memory chip prior to the completion of the first command by the first flash memory chip; and determining whether or not the first flash memory chip has completed the first command.

Method of operating flash memory chips

Disclosed herein is a memory device capable of changing data output modes. According to the present invention, an address that is input to a circuit, which is designed in 8-bit output mode, is internally modified, to operate in 16-bit output mode, and a test operation is performed in 8-bit output mode. As such, two kinds of output mode circuits can be tested in one test equipment. Accordingly, test efficiency can be enhanced and costs can be saved.

Growing community of inventors

Gyeonggi-do, South Korea

Jun Seop Chung