Samsung Electronics Co., Ltd.

Jun-seok Han

Jae-youn Lee

Bong-nam Kim

An AB class buffer amplifier controls quiescent current. The AB class buffer amplifier includes a first current controller and a second current controller. The first current controller sources current to an output node in response to a first logic level of a first signal, and buffers and outputs an input voltage to the output node in response to a second logic level of the first signal. The second current controller sinks the current from the output node in response to a second logic level of a second signal, and buffers and outputs the input voltage to the output node in response to a first logic level of the second signal. The first and second signals are generated at the first logic levels if the input voltage is higher than the output voltage and at the second logic level if the input voltage is lower than the output voltage. The AB class buffer amplifier may further include comparing unit which compares the input voltage with an output voltage from the output node and generates the first and second signals in response to the compared results. The comparing unit includes first and second comparators. Accordingly, the AB class buffer amplifier can drive an external circuit using high currents by freely controlling the amount of quiescent current, and easily sourcing and sinking quiescent current flowing to an output node of the amplifier.

AB class amplifier for controlling quiescent current

A voltage converter is provided. A first cell having a first port, a first node to which a second clock is input, and a first capacitor connected between the first port and the first node, transmits an input signal to the first port in response to a first clock. A second cell having a second port, a second node to which an inverse second clock is input, and a second capacitor connected between the second port and the second node, transmits a signal of the first port to the second port in response to an inverse first clock. A third cell having a final port and a third capacitor coupled between the final port and ground, transmits a signal of the second port to the final port in response to the first clock. The first node and the second node are short-circuited in response to a control signal.

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Yongin, South Korea

Jun-seok Han