Skhynix Inc.

Jun Seo Jang

Jae Hyeong Hong

Soon Sung An

Sung Hwa Ok

Keun Seon Ahn

Eun Ji Choi

Bon Kwang Koo

In Seok Kong

Heon Ki Kim

Gwan Woo Kim

Jung Yeop Lee

Beom Kyu Seo

Jung Hwan Lee

Kwan Su Shon

Yo Han Jeong

Seung Yeop Lee

Chan Keun Kwon

Sun Ki Cho

Hee Jun Kim

Jaehyeong Hong

Dae Ho Yang

Sung Ah Lee

Dong Wook Jang

Young Jo Park

Jong Hun Lim

Byung Joo Hwang

Young Seok Nam

Ji Eun Joo

Nam Hea Jang

Ji Young Lee

Se Min Lee

An internal reference voltage generation device may include a cell array including a plurality of cells which provide reference voltages of different levels. Each of the plurality of cells may include one of a plurality of divider resistors included in a resistor string; a transmission gate configured to output a voltage of a divider node which is connected to the one divider resistor, in response to a select signal; and a unit decoder configured to provide the select signal to the transmission gate.

Internal reference voltage generation device

A receiver circuit includes an input unit configured to receive a reception pattern signal in a training mode, and a reception normal signal in a normal mode, an enable control unit configured to determine whether to activate an enable signal according to the reception pattern signal in the training mode, a first decision feedback equalizer configured to operate in an activation period of the enable signal, and to remove a first post-cursor component for the reception normal signal by calibrating a currently received value based on a previously received value of the reception normal signal, and a second decision feedback equalizer configured to, when the enable signal is in an activated state, remove second to Npost-cursor components for the reception normal signal by adjusting driving abilities of input transistors, to which the currently received value is applied, according to patterns of the reception normal signal.

Receiver circuit and operation method for the same

A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.

Pre-charge control circuit and voltage generation circuit including the same

A calibration device is coupled to a communication line shared by plural devices. The calibration device is configured to perform an iterative eye width scanning by adjusting a set voltage level by a preset level from a first voltage level to a reference center voltage level, wherein the first voltage level corresponds to a cross point where values of signals or data, which are transmitted via the communication lines, are changed in different directions; and determine, as a zero crossing for the signals or the data, a voltage level corresponding to a largest value among a plurality of eye widths obtained through the iterative eye width scanning.

Calibration device and memory device including the calibration device for a high-speed data I/O operation under a low power condition

A duty cycle correction device includes a duty cycle correction circuit and a duty cycle control circuit. The duty cycle correction circuit corrects a duty cycle of an input dock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output dock signal. The duty cycle control circuit generates the duty cycle control signal by detecting a duty cycle of the output clock signal, generates a duty cycle correction completion signal when duty cycle correction is completed, and recorrects the duty cycle of the input clock signal by activating the duty cycle resolution control signal when the duty cycle correction completion signal is activated at an earlier timing than a reference time.

Duty cycle correction device and method

Growing community of inventors

Gyeonggi-do, South Korea

Jun Seo Jang