Fujitsu Corporation

Pfu Limited

Jun Sakurai

Hirohide Sugahara

Akira Kabemoto

Toshiyuki Muta

Takatsugu Sasaki

Takayuki Shimamura

Yozo Nakayama

Junji Nishioka

Satoshi Shinohara

Naohiro Shibata

Hiroshi Sasaki

Takeshi Horie

Toshiyuki Shimizu

Hiroaki Ishihata

Takeshi Kawagishi

Masahiro Yokoyama

Tsutomu Itou

Tatsuya Urushiyama

Kanji Hozumi

A communication system includes a first base station for communicating complying with a first communication protocol, a second base station for communicating by using radio frames complying with a second communication protocol and transmitting synchronization signals complying with the first communication protocol, the synchronization signals synchronizing the transmitted radio frames, and a mobile terminal for communicating according to the process includes: receiving the synchronization signals from the second base station while communicating with the first base station, estimating transmitting timing of the radio frames including symbols on the basis of the received synchronization signals, measuring a receiving signal strength of the symbol on the basis of the estimated timing, and controlling a handover from the first base station to the second base station on the basis of the measurement result by the measurement of the receiving signal strength of the symbol.

Communication system, mobile terminal and communication method

A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Multiprocessor, memory accessing method for multiprocessor, transmitter

A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Coherence apparatus for cache of multiprocessor

Growing community of inventors

Sendai, Japan

Jun Sakurai