Volterra Semiconductor Corporation

Micrel, Incorporated

Jun Ruan

Marco A Zuniga

Yang Lu

Amit Paul

Badredin Fatemizadeh

Jayasimha Prasad

Chiteh Chiang

Craig Cassella

John Xia

William Numann

A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.

Voltage regulators with multiple transistors

The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.

Transistor with buried P+ and source contact

A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.

This document describes systems and techniques related to voltage regulators. The subject matter of this document can be embodied in a method that includes measuring an output current of a switching regulator. The switching regulator includes a high-side transistor and a low side-transistor wherein the high-side transistor and the low-side transistor are driven using a first gate voltage and a second, different gate voltage, respectively. The method also includes adjusting a direct-current (DC) voltage source of the switching regulator such that the first gate voltage is adjusted in accordance with the measured output current.

Voltage regulators with load-dependent bias

Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

Vertical gate LDMOS device

A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.

The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.

A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor; forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask where the first implantation process uses a high implant dose at a low implant energy and the first and second N-type regions form the source and drain regions of the NMOS transistor; forming a channel doped region by a second implantation process using the patterned photoresist as an implant mask where the second implantation process uses a low implant dose at a high implant energy and the channel doped region is formed for adjusting a threshold voltage of the NMOS transistor.

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Santa Clara, CA, United States of America

Jun Ruan