Taiwan Semiconductor Manufacturing Comp. Ltd.

Jun-Nan Nian

Shiu-Ko JangJian

Chi-Cheng Hung

Shih-Chieh Chang

Ting-Chun Wang

Yu-Sheng Wang

Yao-Hsiang Liang

Yu-Ren Peng

Kuan-Ting Liu

Ing-Ju Lee

Ying-Lang Wang

Yu-Ting Lin

Yu-Ku Lin

Hung-Hsu Chen

Jian-Shin Tsai

Ming-Ching Chung

Li-Yen Fang

Jyun-Ru Wu

Hsueh-Han Lu

Chi-Cherng Jeng

Ling-Sung Wang

Chen-Chieh Chiang

Chih-Chung Chang

Chih-Chang Huang

Kun-Ei Chen

Shiu-Ko Jangjian

Yu-Te Hung

Chun-I Liao

Chun-Ju Wu

Embodiments of the present disclosure relate to methods of fabricating conductive features to prevent metal extrusion. Particularly, the conductive feature includes a control layer to reduce grain size of a metal containing layer, thus obtaining a robust structure to decrease extrusion defects. In some embodiments, the control layer is formed between a barrier layer and the conductive feature. In some embodiments, the control layer is formed by adding a control element, such as oxygen, to an upper portion of the barrier layer.

Conductive structures and methods of fabrication thereof

A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, a control layer disposed over the first ILD layer and containing silicon and oxygen, and a resistor wire disposed over the control layer. An oxygen concentration of the control layer is greater than an oxygen concentration of the first ILD layer.

Method of manufacturing semiconductor devices and semiconductor devices

Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.

Semiconductor device structure and methods of forming the same

A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

Method for controlling electrochemical deposition to avoid defects in interconnect structures

An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

Electrochemical plating system and method of using

A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A portion of the metal layer has a crystalline structure. The method further includes filling a remaining portion of the recess with metallic materials, wherein the metallic materials are overlying the metal layer.

N-work function metal with crystal structure

A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive:the suppressor additive:the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.

Method of electroplating metal into recessed feature and electroplating layer in recessed feature

In a method for manufacturing an interconnect structure, a dielectric layer is removed to form a first recess and a second recess. The first recess is below the second recess. A first metal layer is deposited to fill the first recess and a first portion of the second recess. A carbon-containing layer is deposited over the first metal layer to fill a second portion of the second recess, which is over the first portion. A second metal layer is deposited over the carbon-containing layer to fill a third portion of the second recess, which is over the second portion. A carbon concentration of the carbon-containing layer is greater than a carbon concentration of the first metal layer and a carbon concentration of the second metal layer, and the carbon concentration of the first metal layer is substantially the same as the carbon concentration of the second metal layer.

Formation of copper layer structure with self anneal strain improvement

A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive: the suppressor additive: the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.

A copper layer structure includes a first copper layer, a second copper layer and a carbon-rich copper layer. The second copper layer is disposed over the first copper layer. The carbon-rich copper layer is sandwiched between the first copper layer and the second copper layer. A carbon concentration of the carbon-rich copper layer is greater than a carbon concentration of the first copper layer and a carbon concentration of the second copper layer.

A system and method for reducing cross-talk in complementary metal oxide semiconductor back side illuminated image sensors is provided. An embodiment comprises forming a grid around the pixel regions on an opposite side of the substrate than metallization layers. The grid may be formed of a material such as tungsten with a (110)-rich crystalline orientation. This orientation helps prevents defects that can occur during patterning of the grid.

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Tainan, Taiwan

Jun-Nan Nian