Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Jun Nakai

Noboru Shibata

Kosuke Yanagidaira

Yoshikazu Harada

Yoshikazu Takeyama

Yuko Utsunomiya

Hayato Konno

Hiroe Kami

Yuji Nagai

Kenri Nakai

Yuki Kanamori

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

Nonvolatile semiconductor memory device which performs improved erase operation

A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.

Semiconductor memory device and memory system configured to perform tracking read on first memory cells followed by shift read on second memory cells using read voltage correction value determined during the tracking read

A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N&#x2212;1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.

Semiconductor memory device

A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.

Power supply circuit and semiconductor memory

Growing community of inventors

Yokohama, Japan

Jun Nakai