Hitachi, Ltd.

Nippon Telegraph and Telephone Corporation

Jun Miyake

Yasunori Yamaguchi

Tsuyoshi Abe

Katsumi Takahashi

Masahisa Kawashima

Noriaki Saito

Masayoshi Nakao

Shingo Kinoshita

Yukio Tsuruoka

Fumitaka Hoshino

Akiko Fujimura

A recipient identifier and communication condition information stored in a recipient-identifier storing unit are encrypted by an identifier-for-disclosure creating unit of a recipient terminal to create an identifier-for-disclosure. An identifier-for-disclosure notifying unit notifies a sender terminal of the identifier-for-disclosure. When a communication request using the identifier-for-disclosure is sent from the recipient terminal, a restoring unit of a relay system extracts the communication condition information from the identifier-for-disclosure. Only when communication conditions included in the communication condition information are satisfied, communication between the recipient terminal and the sender terminal is established.

Email system restoring recipient identifier based on identifier-for-disclosure for establishing communication between sender and recipient

When an alias mail having an alias address X as a destination is received from an originator terminal, an alias mail relay server restores a recipient address R and an alias address generation argument C, generates a reply destination address Y including the generation argument C restores and an originator address S, and replaces the destination and a transmission source with the recipient address R and Y to transfer the alias mail to a recipient terminal. On the other hand, when a reply mail is received from the recipient terminal, a remailer restored the originator address S and the generation argument C from Y, regenerates X from the generation argument C restored and the recipient address R, and replaces a destination and a transmission source with the originator address S and X to transfer the reply mail to the originator terminal.

Mail distribution system, mail distribution method, and mail distribution program

In a driving circuit for generating driving signals for controlling and switching on and off a first output element employed in an output circuit for generating a high-level output signal and a second output element employed in the output circuit for generating a low-level output signal in a mutually complementary manner, the conductance of the driving circuit is controlled so that it increases gradually with the lapse of time. By sequentially controlling the conductance of the driving circuit for generating the driving signals, the rates of change of the driving signals can be controlled in a smooth and stable manner and output currents can thus be changed smoothly to result in high-speed operation of an output signal with a reduced amount of noise.

Low noise MOSFET employing selective drive signals

A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

Semiconductor memory device

A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the long logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

A single chip semiconductor memory device having an arithmetic circuit to conduct plural kinds of arithmetic operations and a mask control circuit for inhibiting a substantial change in data in memory irrespective of the operations of the arithmetic circuit when it is brought into a masking state. The semiconductor memory device takes a preset operation mode for receiving from the outside a control signal for the arithmetic circuit and the mask control circuit. This control signal for the arithmetic circuit and the mask control circuit, which is given to the semiconductor memory device when in the preset operation mode, is latched in the semiconductor memory device until the device is brought again into the preset operation mode.

Growing community of inventors

Musashino, Japan

Jun Miyake