Renesas Electronics Corporation

Kajima Corporation

Yacmo Kabushiki Kaisha

Renesas Technology Corp.

Copal Company Limited

Jun Matsushima

Takayuki Suzuki

Yoichi Maeda

Hideshi Maeno

Toru Kasai

Hideo Hayashi

Hiroyuki Iwata

Kenichi Yano

Ryuichi Kamimura

Masamitsu Miyamura

Katsuhisa Kanda

Nobumitsu Funaki

Hiroyuki Sasaki

Makoto Saen

Shigekazu Nakamura

Kenji Wakazono

Hiroki Wada

Tomoyoshi Ujii

Yuri Ikeda

Yoshikazu Aoto

Tetsuto Kageyama

Yoshinori Nishida

A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor deviceincludes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Semiconductor device and method of controlling self-diagnosis

An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Semiconductor device and diagnostic method therefor

There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Semiconductor device and diagnosis method thereof

A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

Semiconductor device and scan test method including writing and reading test data

In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.

Semiconductor device, electronic control system and method for evaluating electronic control system

A semiconductor device () according to the present invention includes a circuit to be tested () having a scan chain, and a first test control device () and a second test control device () that perform a scan test of the circuit to be tested by using the scan chain. The second test control device () performs a second scan test of the circuit to be tested (), the circuit to be tested () gives the first test control device () an instruction to perform a first scan test after the second scan test is performed, and the first test control device () performs a first scan test of the circuit to be tested () in response to an instruction from the circuit to be tested ().

Semiconductor device and diagnostic test method for both single-point and latent faults using first and second scan tests

It is possible to reduce the number of test point circuits to be inserted necessary to accomplish a target fault coverage, to suppress an increase in an area overhead, and to reduce a test time. A test point circuit according to an embodiment constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock, the first operation result having been captured by a test point circuit at a previous stage or a last stage of the scan chain in the first capture clock.

Test point circuit, scan flip-flop for sequential test, semiconductor device and design device

An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.

Apparatus and method for designing semiconductor device, and semiconductor device

The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided. With the configuration, even in the case where the number of processors increases, the invention can flexibly address the increase.

Test access control for plural processors of an integrated circuit

A device to control vertical vibration of a building caused by seismic disturbance. Air springs are positioned and secured between the building foundation and the building superstructure to attenuate vertical vibration of the building. Vertical support rails are secured to the foundation and/or to the building superstructure on opposite sides of, and adjacent to, the air springs. Horizontal connecting brackets are rigidly secured to the air springs and slidably secured to the adjacent rails. The brackets restrain horizontal deflection of the air springs without interfering with vertical reciprocation of the air springs.

Vertical vibration control device

A torque sensor for use in detecting torsion of a power steering device or the like of a vehicle. The torque sensor is provided with a first shaft supported for rotation about its axis in a casing, a permanent magnet secured to the first shaft, a second shaft supported for rotation about its axis in the casing and disposed in end-to-end relationship to the first shaft, a connecting shaft for connecting the first shaft and the second shaft, a magnetic core secured to the second shaft and a magnetism sensor secured to the casing and sandwiched between ring-shaped magnetic members disposed in the vicinity of the outer peripheral face of the magnetic core so that a change in magnetic flux which is caused by the relative displacement of the permanent magnet and the magnetic core is detected by the magnetism sensor as the direction of a variation in the relative position of and the amount of variation in a displacement of the first shaft and the second shaft about the axis of rotation of the first and second shafts.

Growing community of inventors

Tokyo, Japan

Jun Matsushima