Altera Corporation

Oracle America, Inc.

Ebara Technologies Incorporated

Sun Microsystems, Inc.

Hoshizaki America, Inc.

Multiplanar Technologies Incorporated

Jun Liu

Qi Xiang

Albert Ratnakumar

Irfan Rahim

Jeffrey Xiaoqi Tung

Yanzhong Xu

Andy Louie Lee

Jeffrey T Watt

Shankar Sinha

Srinivas Perisetty

Dennis L Wendell

Shih-Lin S Lee

Gerard Moloney

Yolin Lih

Ajay Bhatia

Daniel Fung

Shyam Sundar Balasubramanian

Mark Chan

Cormac Walsh

Wilson Wong

Bonnie I Wang

Simardeep Maangat

William Bradley Vest

Yow-Juang Bill Liu

Jiro Kajiwara

Lu Zhou

Huey-Ming Wang

Alejandro Reyes

Jeremy Neill

Junsheng Yang

Mao Du

Peter Lao

Ernesto Saldana

Christopher L Kight

Yanzhong Yu

Kunihiko Sakurai

A Ernesto Saldana

Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Integrated circuits with asymmetric and stacked transistors

Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory cell transistors and the pass transistors may be formed using multiple strips of oxide definition (OD) regions coupled in parallel. The multiple OD strips may have reduced widths. The ratio of the distance from adjacent OD strips to a given OD strip to the width of the given OD strip may be at least 0.5. Forming memory circuitry transistors using this multi-strip arrangement may provide increased levels of stress that improve transistor performance. Each OD strip may have a reduced width that still satisfies fabrication design rules. Forming OD regions having reduced width allows the pass transistors to be overdriven at higher voltage levels to further improve transistor performance.

Memory element circuitry with minimum oxide definition width

An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second transistors coupled in series. The first transistor receives an input signal and the second transistor receives a pulsed voltage signal. Furthermore, a method to operate the IO buffer circuit is also disclosed.

Input-output buffer circuit with a gate bias generator

Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

Method of fabricating integrated circuit transistors with multipart gate conductors

A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC.

Method of using a PMOS pass gate

A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.

Memory circuit with PMOS access transistors

Input-output (IO) buffer circuitry is provided that is operable to drive signals off an integrated circuit. The input-output circuitry may include an input-output driver having an asymmetric transistor and/or a low-threshold voltage transistor. The asymmetric transistor may include a first source-drain region at a first dopant concentration level and a second source-drain region at a second dopant concentration level. The first dopant concentration level and the second dopant concentration level may be different. The IO buffer circuitry may be able to prevent issues with regards to hot carrier injection when driving signals with elevated voltages. The IO buffer circuit may also be manufactured without increasing the overall cost.

Input-output buffer circuitry with increased drive strength

Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

Integrated circuits with asymmetric pass transistors

An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

PMOS pass gate

Integrated circuit transistors with multipart gate conductors

Memory element circuitry with reduced oxide definition width

Integrated circuits such as programmable integrated circuits may have configuration random-access memory elements. The configuration random-access memory elements may be loaded with configuration data to customize programmable circuitry on the integrated circuits. Each memory element may have a bistable element that is powered using a positive power supply voltage and a negative power supply voltage. Programmable transistors in the programmable circuitry may have gates coupled to outputs of the bistable elements. The programmable transistors may have gate insulators that are thinner than gate insulators in the transistors of the bistable elements and may have threshold voltages of about zero volts. During operation, some of the configuration random-access memory elements may supply negative voltages to their associated programmable transistors so that the programmable transistors are provided with gate-source voltages of less than zero volts.

Programmable integrated circuit with thin-oxide passgates

Integrated circuits may be provided that include memory elements that produce output control signals and corresponding programmable logic circuitry that receives the output control signals from the memory elements. The memory elements may include bistable storage elements formed from circuits such as cross-coupled inverters. The inverters may include n-channel metal-oxide-semiconductor transistors with p-metal gate conductors and n-channel metal-oxide-semiconductor transistors with p-metal gate conductors. These gate conductor assignments are the reverse of the gate conductor assignments used in the n-channel and p-channel transistors in other circuitry such as the programmable logic circuitry. The reversed gate conductor assignments increase the threshold voltages of the transistors in the memory elements to improve reliability in scenarios in which the memory elements are overdriving pass transistors in the programmable logic circuitry.

Memory element transistors with reversed-workfunction gate conductors

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Milpitas, CA, United States of America

Jun Liu