No. 24 Research Institute of China Electronics Technology Group Corporation

China Electronic Technology Corporation, 24th Research Institute

Chongqing Gigachip Technology Co. Ltd.

Jun Liu

Dongbing Fu

Guangbing Chen

Ruzhang Li

Gangyi Hu

Liang Li

Mingyuan Xu

Jianan Wang

Xiaofeng Shen

Xi Chen

Xingfa Huang

Youhua Wang

Junan Zhang

The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M), a second MOS transistor (M) and a capacitor (C); a drain of the first MOS transistor (M) is connected to a negative terminal (CLK&#x2212;) of a differential clock, a gate of the first MOS transistor (M) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M) is connected to a drain of the second MOS transistor (M); a gate of the second MOS transistor (M) is connected to the negative terminal (CLK&#x2212;) of the differential clock, and a source of the second MOS transistor (M) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.

Differential clock cross point detection circuit and detection method

The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

High speed duty cycle correction and double to single ended conversion circuit for PLL

Growing community of inventors

Chongqing, China

Jun Liu