Globalfoundries Inc.

Globalfoundries U.S. Inc.

Jun Lian

Haiting Wang

Min-Hwa Chi

Jin Ping Liu

Seung Yeon Kim

Wei Hua Tong

Yan Ping Shen

Tien-Ying Luo

Feng Zhou

Haoran Shi

Sipeng Gu

Yanping Shen

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. The present disclosure provides a semiconductor device including a first device region and a second device region. The first device region includes a first metal layer, a first via structure over the first metal layer, a second via structure over the first via structure, and a second metal layer over the second via structure. The first via structure and the second via structure electrically couple the second metal layer to the first metal layer. The second device region includes a third metal layer, a contact structure over the third metal layer, a memory cell structure over the contact structure, and a fourth metal layer over the memory cell structure. The first via structure and the contact structure are made of the same material.

Via structures for use in semiconductor devices

Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Conformal nitridation of one or more fin-type transistor layers

One method includes forming first and second devices by forming a first layer of gate insulation material having a first thickness for the first device, forming a layer of high-k insulation material having a second thickness that is less than the first thickness for the second device and forming first and second metal-containing gate electrode structures that contact the first layer of gate insulation material and the high-k insulation material. A device disclosed herein includes first and second semiconductor devices wherein the first gate structure comprises a layer of insulating material having a first portion of a first metal layer positioned on and in contact with the layer of insulating material and a second gate structure comprised of a layer of high-k insulation material and a second portion of the first metal layer positioned on and in contact with the layer of high-k insulation material.

Methods of forming semiconductor devices with different insulation thickness on the same semiconductor substrate and the resulting devices

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Mechanicville, NY, United States of America

Jun Lian