Samsung Electronics Co., Ltd.

Jun Kyu Yang

Young Jin Noh

Bio Kim

Woo Jin Jang

Kyong Won An

Jae Ho Choi

Jae Young Ahn

Eun Yeoung Choi

Jae Hyun Yang

Dong Chul Yoo

An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

Integrated circuit memory devices having impurity-doped dielectric regions therein and methods of forming same

A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.

Semiconductor device

Growing community of inventors

Seoul, South Korea

Jun Kyu Yang