Skhynix Inc.

Jun Ku Ahn

Sung Lae Cho

Gwang Sun Jung

Jong Ho Lee

Uk Hwang

Hyung Keun Kim

Jun Young Lim

Young Ho Lee

Beom Seok Lee

Hwan Jun Zang

Woo Tae Lee

Sang Hyun Ban

UK Hwang

Ye Cheon Cho

Disclosed is a chalcogenide material including germanium (Ge), selenium (Se), arsenic (As), silicon (Si) and indium (In). In the chalcogenide material, a content of selenium (Se) is 49 at % to 56 at %, a content of indium (In) is 1.1 at % or less, and a sum of contents of germanium (Ge) and silicon (Si) is 18 at % to 21 at %.

Chalcogenide material and semiconductor device including the same

A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.

Semiconductor device and manufacturing method of the semiconductor device

A semiconductor device may include a first electrode, a second electrode, an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall, a variable resistance layer formed in the opening, and a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode. The variable resistance layer includes a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area. The variable resistance layer maintains an amorphous state during a program operation.

Semiconductor device and method of manufacturing semiconductor device

A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 μm to 5 μm, and a first ratio of an average grain diameter of carbon after the sintering is Y (μm) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (μm), an average grain diameter of carbon after the sintering is Y (μm), and a content of carbon is Z (at %).

Sputtering target including carbon-doped GST and method for fabricating electronic device using the same

A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.

Chalcogenide material, variable resistance memory device and electronic device

An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed at intersection regions of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first and second directions; and a heat sink positioned between two memory cells adjacent to each other in a diagonal direction with respect to the first and second directions.

Electronic device and method of fabricating the same

A sputtering target includes: a base configured to transfer heat in a basal plane direction; and a first heat sink disposed on a sidewall of the base, the first heat sink configured to transfer heat along a direction that is different from the basal plane direction.

Growing community of inventors

Hwaseong, South Korea

Jun Ku Ahn