Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Jun Kitano

Susumu Hatano

Kunio Uchiyama

Osamu Nishii

Takeshi Wada

Kanji Oishi

Hirokazu Aoki

Yasushi Takahashi

Masayasu Kawamura

Shin'ichi Ikenaga

Fujio Yamamoto

Kenji Nishimoto

Michihiro Mishima

Jun Miyake

Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

Semiconductor memory device

In a serial memory which internally converts serial input data into parallel data and writes the data into a memory array two or more bits at a time, and which reads data two or more bits at a time from the memory array and internally converts the read data into serial data for output, circuits are provided that allow selective reversing of the order of parallel conversion on the serial input data and of serial conversion on the parallel data read from the memory array. This serial memory is also provided with a memory controller to reverse the ascending or descending order of the access address for the memory array in the read and write operations.

Serial memory

Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.

Multiprocessor cache system having three states for generating

Growing community of inventors

Kodaira, Japan

Jun Kitano