Oki Electric Industry Co., Ltd.

Tokyo Ohka Kogyo Co., Ltd.

Jun Kanamori

Toshiyuki Nakamura

Akira Takahashi

Motoki Kobayashi

Atsushi Matsushita

Kousuke Hara

Mitsuaki Minato

Hideaki Matsuhashi

Yoshiaki Katakura

Yoshihiro Koga

Yoko Kajita

Shinichi Omori

Mamoru Yokoyama

A method of fabricating a semiconductor device having a silicon layer disposed on an insulating film. Oxygen ions are implanted into selected parts of the silicon layer, which are then oxidized to form isolation regions dividing the silicon layer into a plurality of mutually isolated active regions. As the oxidation process does not create steep vertical discontinuities, fine patterns can be formed easily on the combined surface of the active and isolation regions. The implanted oxygen ions cause oxidation to proceed quickly, finishing before a pronounced bird's beak is formed. The isolation regions themselves can therefore be narrow and finely patterned.

Semiconductor device fabrication method using oxygen ion implantation

The present invention aims to provide a method of manufacturing a semiconductor device having an SOI structure, which is capable of setting an etching process so as to cause contact etching to widely have a process margin even in a semiconductor elemental device using an extra-thin SOI layer. The present method is a method of manufacturing a fully depleted-SOI device. A cobalt layer is formed on an SOI layer. Cobalt is transformed into a cobalt silicide layer by heat treatment. An interlayer insulating film is formed on the cobalt silicide layer, and a contact hole is defined in the interlayer insulating film by dry etching. As an etching gas used in such a dry etching step, a CHF3/CO gas is used. An etching condition is set through the use of a dry etching rate held substantially constant by use of the etching gas. Described specifically, etching time is suitable set.

Method of manufacturing semiconductor device having SOI structure

A field oxide film for element isolation is formed on an SOI substrate having a silicon layer formed on an insulating layer, an active nitride film is wet-etched to reduce its film thickness to a value small enough to allow the edge of the silicon layer to become exposed and ions of a channel stopping impurity are implanted only into the edge of the silicon layer through self-alignment either vertically or at an angle by using the active nitride film as a mask. Through this manufacturing method, a field effect transistor which achieves a small gate length, is free from the adverse effect of a parasitic transistor and thus does not readily manifest a hump, and allows a reduction in the distance between an nMOS and a pMOS provided next to each other is realized.

Method for manufacturing field effect transistor

In a method for fabricating a semiconductor device, a silicide material is formed at least on the surface of an area to be silicided. Then, a first RTA (Rapid Thermal Annealing) process is performed to form a first-reacted silicide region. Next, a supplemental silicon layer is formed over the entire surface; and a second RTA process is performed to form a second-reacted suicide region.

Semiconductor device and method for fabricating the same

In a semiconductor device and method of manufacturing thereof, a semiconductor device having an SOI structure is provided with a capacitor including a first electrode in an SOI layer, a second electrode opposing the first electrode, and a dielectric film therebetween. An isolation region is provided as contained in the SOI layer to electrically isolate the first electrode from remaining areas of the SOI layer, such as active areas or the like. The method includes forming the isolation regions in the SOI layer, forming the first electrode in the SOI layer as electrically isolated from the remaining areas of the SOI layer by the isolation regions, forming the dielectric film on the first electrode, and forming the second electrode on the dielectric film opposite the first electrode.

Semiconductor device and method for manufacturing semiconductor device

In fabricating a capacitor portion of a semiconductor device, after forming an upper electrode, a resist pattern for forming a lower electrode is formed and etching processing of an insulating film layer and a first metal layer is carried out. Thus, the lower electrode and a wiring pattern can simultaneously be formed by etching the insulating film layer and the first metal layer after forming a resist pattern one time, without a resist pattern directly formed on the first metal layer.

Method of fabricating semiconductor device equipped with capacitor portion

In a method for fabricating a semiconductor device, a silicide material is formed at least on the surface of an area to be silicided. Then, a first RTA (Rapid Thermal Annealing) process is performed to form a first-reacted silicide region. Next, a supplemental silicon layer is formed over the entire surface; and a second RTA process is performed to form a second-reacted silicide region.

Semiconductor device with self-aligned areas formed using a supplemental silicon overlayer

A gate dielectric film 102, gates 104a formed of polysilicon, an offset oxidation film 106a formed of silicon nitride, and an etching stopper nitride film 108a formed of silicon nitride are sequentially formed on a silicon substrate 100, and side walls 110 formed of silicon nitride are formed on side surfaces of the offset oxidation film 106a and the etching stopper nitride film 108a. Since an oxidation polysilicon film 112 having better insulating characteristics than silicon nitride is formed on the side surfaces of the gates 14a by oxidation processing, the cross sectional thickness of the oxidation polysilicon film 112 can be made thin. A sum value of two times the cross sectional width of the etching stopper nitride film 108a and the cross sectional width of the side walls 110 is larger than the cross sectional width of the gates 104a, and the gates 104a are not etched when forming contact holes 116.

Semiconductor device and method of manufacturing the same

A plasma processing apparatus for processing a workpiece such as a semiconductor wafer in a plasma includes a downstream- or coaxial-type chamber for housing the workpiece. A first sheet-like electrode is mounted on an outer circumferential surface of the chamber and electrically connected to a high-frequency power supply, and a second sheet-like electrode is mounted on the outer circumferential surface of the chamber and connected to ground. The first and second sheet-like electrodes are spaced in confronting relationship from each other circumferentially of the chamber across or along the axis thereof. The first and second sheet-like electrodes have respective axial or circumferential arrays of successive teeth, such as rectangular comb teeth, extending circumferentially or axially of the chamber and respective axial or circumferential arrays of successive recesses which complementarily receive the teeth, respectively, in an interdigitating pattern. The teeth have respective edges spaced from the corresponding edges of the recesses by a substantially uniform gap.

Plasma processing apparatus

A multilevel metallization structure for a semiconductor device having an antireflective film and a migration resistant film. The antireflective film is formed on a lower metallization and an dielectric inter-level film is formed on the antireflective film. The dielectric inter-level film has an opening hole for exposing the surface of the lower metallization. The migration resistant film is formed on the dielectric inter-level film and the surfaces of side walls of the opening hole. The upper metallization is formed on the migration resistant film and inside the opening hole so as to directly connect to the lower metallization.

Semiconductor device multilayer metal layer structure including

In a process for fabricating a semiconductor device having a trench at the surface of a semiconductor substrate, a first mask layer is formed to have an opening whose side is set back from an area where the trench will be formed, a second mask layer is formed on the side of the opening of the first mask layer with an opening corresponding to the area where the trench will be formed, and an etching is performed using the first and the second mask layer as a mask to form the trench.

Process for fabricating a semiconductor device

An etching method is disclosed including a process of improving the adhesiveness between a positive resist layer and a material layer to be etched. The material layer to be etched is dipped in an organic solvent. The structural body thus-produced in the aforesaid process is placed in the atmosphere of Freon vapor to dry the material layer to be etched. The positive resist film is then formed on the surface of the material layer to be etched.

Growing community of inventors

Tokyo, Japan

Jun Kanamori