Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Jun Kajiwara

Masayoshi Kinoshita

Shiro Sakiyama

Katsuji Satomi

Katsuhiro Ootani

Akira Yamamoto

Shinichi Yamamoto

Toshinobu Hatano

Kenji Arakawa

Hiroyuki Nakahira

Toshiyuki Nakashima

Shirou Sakiyama

Hiroo Yamamoto

Toshiya Kogishi

Toru Iwata

Kiyoshi Morimoto

Toshiya Fujii

Kiyoyuki Morita

Michihito Ueda

Kenji Toyoda

Toshiyuki Moriwaki

Yoshihisa Shimazu

Ryouichi Nagayoshi

A solid-state image sensing apparatus including a solid-state image sensing device and a signal processing circuit. The solid-state image sensing device includes: a vertical transfer unit, composed of transfer columns corresponding to columns of the light-to-electric conversion elements, operable to transfer, in a vertical direction, signal charges read out from the light-to-electric conversion elements; a horizontal transfer unit operable to receive the signal charges from the vertical transfer unit and transfer them in a horizontal direction. The signal processing circuit converts the signal charges from the horizontal transfer unit into pixel data, and rearranges it into a two-dimensional array. In the rearrangement, the signal processing circuit, per transfer of one piece of pixel data, cyclically selects a line memory out of three line memories, writes a piece of pixel data into the selected line memory, or reads a row of pixel data from the selected line memory.

Pixel arranging apparatus, solid-state image sensing apparatus, and camera

A charge transfer implemented by a transfer section for transferring charges stored in image sensor elements along one direction on a surface where the image sensor elements are disposed is halted for a predetermined length of time. The charges are transferred from the transfer section without reading the charges from the image sensor elements after the charge transfer is halted for the predetermined length of time. A position where a defect is generated in an image pickup sensor is identified based on signal levels of the transferred charges. A defective signal level of the image pickup sensor generated on a line including the defect-generating position and in parallel with the one direction is corrected. As a result of the foregoing process, a display failure is precisely corrected.

Method for detecting vertical transfer defects in image sensors

A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.

Multi-chip module, semiconductor chip, and interchip connection test method for multi-chip module

A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.

Multichip module structure

A potential generating circuit comprises a capacitor ( ); a ferroelectric capacitor ( ) connected in series to the capacitor ( ); an output terminal ( ); a capacitor ( ) for grounding the output terminal ( ); a switch ( ) for connecting a connecting node ( ) between the two capacitors ( ) to the output terminal ( ); and a switch ( ) for connecting the connecting node ( ) to the ground; wherein during a first period, with the switches ( ) and ( ) placed in the OFF state, a terminal ( ) is provided with a positive potential and a terminal ( ) is grounded; wherein during a second period following the first period, the terminal ( ) is grounded and the switch ( ) is placed in the ON state; wherein during a third period following the second period, the switch ( ) is placed in the OFF state, the switch ( ) is placed in the ON state, and the terminal ( ) is provided with a positive potential; wherein during a fourth period following the third period, the terminal ( ) is grounded; and wherein the first through fourth periods are repeated.

Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof

A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground. Until the output voltage from the comparison circuit is higher than the threshold voltage of the PMOS transistor, the PMOS transistor remains OFF, thereby canceling the input of the output voltage signal from the voltage division circuit to the comparison circuit. Thus, without using external components, the signal is prevented from being erroneously output due to the output voltage from the voltage division circuit rising over, without crossing, the reference voltage from the reference voltage circuit during a sharp rise of the power supply voltage.

Power supply voltage detection circuit

A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.

Method for designing power supply circuit and semiconductor chip

A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.

Semiconductor chip and multi-chip module

During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.

Power source system for reducing power consumption in an intermittent mode of operation

A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal as logical terminals, the function information of the standard cell containing logical information or delay information of the power supply terminal relative to an output terminal, or function information of macro cells which are functional circuits forming a logical device, each of the macro cell comprising at least one of power supply terminals as logical terminals, the function information of the macro cell containing logical information or delay information of said power supply terminals relative to an output terminal. A design aiding system uses the cell library database to execute logical simulation, etc.

Cell library database and design aiding system

Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.

Semiconductor chip, set of semiconductor chips and multichip module

Method of designing power supply circuit and semiconductor chip

In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors through having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor

Switching regulator and LSI system

The switching regulator of a synchronous rectifying mode comprises the first and second switches SW,, SW,arranged in series between the power source Vdd and the ground Vss, the switch control unit,which controls the on-off operation of the switches SW,, SW,, and the smoothing circuit,which smoothes the output node potential Vnd. When the signal Sc,indicates that the output node potential Vnd goes below the first reference potential Vr,which is the reference to detect the occurrence of the inrush current while the first switch SW,is in the ON state, the control circuit,turns off the first switch SW,. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW,, so that it is unnecessary to provide a resistance element for detecting the inrush current.

Switching regulator DC/DC converter, and LSI system provided with switching regulator

A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source. Accordingly, during the initial operation of the power circuit, the gate potential of the limiting transistor gradually decreases while the gate-source voltage of the output transistor gradually increases. As a result, the generation of the inrush current can be suppressed.

Growing community of inventors

Kyoto, Japan

Jun Kajiwara