Taiwan Semiconductor Manufacturing Comp. Ltd.

Jun-Jyeh Hsiao

Shao-Yu Wang

Chien-Te Wu

Louis Chaochiuan Liu

Wen-Hsiang Huang

Cheng-Yu Lu

Hsiao-Pin Su

System and method for integrated circuit (IC) design using silicon intellectual property (IP) libraries that permits the protecting of the designs of circuits in the silicon IP while allowing correctness verification of the IC design. A preferred embodiment comprises a phantom cell (for example, phantom cell) that contains circuit elements (for example, circuit element EL-A) connected to each input/output pin of the phantom cell. The inclusion of the circuit elements permits an engineering design tool to check for improperly connected wiring.

System and method for protecting and integrating silicon intellectual property (IP) in an integrated circuit (IC)

A layout structure and method are described for the layout of chips having libraries of standard cells which minimizes voltage fluctuations on power buses caused by switching circuits in the standard cells. Typically these standard cells are arranged in a row between two power buses. In this invention the standard cells are partitioned into first cells and second cells which can be combined to form the standard cell circuit. The first cells are arranged in a first row and the second cells are arranged in a second row. A first power bus is located above the first row of first cells and a second power bus is located below the second row of second cells. The first power bus and second power bus are electrically connected together. The first power bus supplies a first power supply voltage to the first cells and the second power bus supplies the first power supply voltage to the second cells. A third power bus is located between the first row of first cells and second row of second cells and supplies a second power supply voltage to the first and second cells. The layout can be accomplished automatically using a computer program.

Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation

Antenna diodes used to correct antenna rule violations during the design and formation of integrated circuits are defined within filler cells laid out on the IC chip following the layout of standard electronic module cells and routing of electrical conductors on the chip. The filler cells are disposed in gaps between standard cells containing the electronic modules. The diodes are formed in unconnected pairs that are selectively connected to each other and to an adjacent conductor in order to correct antenna rule violations. Low current leakage is achieved as a result of the use of a fewer number of diode circuits, and the fact that they remain unconnected until used to correct an antenna rule violation.

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Hsin-Chu, Taiwan

Jun-Jyeh Hsiao