Samsung Electronics Co., Ltd.

Jun-jin Kong

Yong-Woo Park

Sung-Han Choi

Sung-han Choi

Jae-Hong Kim

Suk-jin Kim

Hong-Seok Kim

Jae-wook Lee

Dae-won Kim

Soo-jung Ryu

Jeong-Wook Kim

Jung-Il Park

Chan-Geu Park

Taek-won Kwon

Won-hee Chung

Jun-rim Choi

Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.

Loop accelerator and data processing system having the same

A device for detecting in a receiver whether any transmission errors have occurred in the received CRC code, in a case that a transmitter transmits the CRC code created by sequencing the parity bits, which are generated using the generator polynomial, in the reverse order and appending them to the message bits. The device comprises a division unit for dividing the message bits by the parity bit generator polynomial to form the remainder, a comparison unit for bitwise comparing the remainder bits with the reverse ordered parity bits, and a decision unit for deciding whether transmission errors have occurred in the CRC code based on the results of the comparison unit. According to the present invention, the transmission errors in the received CRC code are effectively detected, when the CRC code includes the parity bits sequenced in the reverse order, unlike the conventional normal order.

Device and method for detecting errors in CRC code having reverse ordered parity bits

A high speed Viterbi detector for an optical disk system, includes a frequency dividing unit for generating an auxiliary clock at one-third of the main clock frequency, a branch metric calculation unit for calculating each of a plurality of branch metrics, a serial-to-parallel converting unit for outputting each of the branch metrics at the main clock frequency in units of 3 state bits, an addition/comparison/selection unit for adding the branch metrics and previously stored state metrics and for comparing the addition results to select and output the minimum of the addition results as a new state metric, and for outputting a corresponding path selection signal, at the auxiliary clock frequency, a path memory for storing the path selection signal and for outputting parallel data corresponding to the path selection signal, at the auxiliary clock frequency, and a parallel-to-serial converting unit for converting the path memory output into serial data.

Viterbi detector for optical disk system

A two-step Viterbi algorithm decoder for tracing the survivor path and the concurrent path and updating a soft decision value, including a soft output Viterbi algorithm state metric unit (SOVA-SMU), which is constructed of registers and multiplexers, instead of a memory for storing survivor information for all states.

Two-step soft output viterbi algorithm decoder using modified trace back

An apparatus for providing and storing a state metric which is used for an add-compare-select (ACS) operation in a Viterbi decoder using a number of ACS units in order to enhance decoding speed. A state metric memory in Viterbi decoder uses a two-port memory, in which a memory bank for reading and writing a state metric of a first half among the N state metrics generated in a ACS unit and two memory banks for alternately reading and writing the state metric of the second half whenever a codeword is input, are incorporated into a single memory. As a result, the storage capacity for storing the state metrics can be greatly reduced as compared to a conventional apparatus.

Viterbi decoder

A quality calculator apparatus for Viterbi-decoded data using zero-state metrics. The quality calculator for the Viterbi-decoded data includes: a Viterbi decoder which outputs zero-state metrics of input demodulated data according to the four possible transmission rates of FULL, HALF, QUARTER and 1/8; a register which stores respective zero-state metrics output from the Viterbi decoder; and a quality evaluation unit which reads the zero-state metrics stored in the register to evaluate the Viterbi-decoded data based on the zero-state metrics and which determines the actual transmission rate to be the one among the possible transmission rates which has the least zero-state metrics. The zero-state metrics of the demodulated data input to the Viterbi decoder are used as a quality evaluation parameter so that the quality evaluation can be correctly achieved to avoid errors in determining of the transmission rate, as compared to a quality calculator using a bit error ratio as the quality evaluation parameter.

Quality calculator apparatus for use with Viterbi-decoded data using

An improved programmable control sequencer and a method for its map allocation capable of reducing the size of program RAM used in a disk controller of a magnetic disk drive storage system, thereby efficiently reducing a work load of a microcontroller unit in the disk controller. The map allocation method is performed in a program random access memory having a 32.times.2 byte size of data storage area in the disk controller, the program random access memory being provided with the sequencer map allocation including a branch field, a next address/count field, an output field, a gate field, a field region and a data selection field. The branch field is provided with branch condition or count field enable information. The next address/count field selectively has a next address or a count value according to the branch condition. The output field is usable for testing synchronization outside the programmable control sequencer and the gate field for performing Read/Write gate control and making increase of target sector number and decrease of disk sector transmit count. The field region represents ECC/CRC block and CDR return and the data selection field is usable for comparing data from any data register with data read of the disk, thereby processing the data according to the compared result.

Programmable control sequencer of disk controller and method for map

A Viterbi decoder which operates a plurality of states at one time to thereby decode a plurality of channels at an increased speed. The decoder includes a branch metric calculating unit which receives convolutional data and calculates a plurality of branch metrics. A branch metric allocating unit allocates the plurality of branch metrics as even and odd branch metrics. A state metric storing unit stores a current state metric and allocates a plurality of state metrics as even and odd state metrics. First and second add-compare-select (ACS) units perform addition, comparison, and selection on the even branch and state metrics, and select paths having optimum distances. Third and fourth ACS units perform addition, comparison, and selection on the odd branch and state metrics, and select paths having optimum distances. A path tracing logic unit traces the path selection information selected in the first through fourth ACS units, and outputs decoded data. A path storing unit stores a path selection signal generated and selected in the path selection information controller.

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Sungnam, South Korea

Jun-jin Kong