Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Postech Academy-Industry Foundation

Soongsil University

Jun-Jin Kong

Hong-Rak Son

Eun-chu Oh

Pil-sang Yoon

Jae-Hong Kim

Kyoung-Lae Cho

Chang-Kyu Seol

Seong-Hyeog Choi

Seung-Hwan Song

Kyeong-Cheol Yang

Dong-Min Shin

Jong-Seon No

Yong-June Kim

Hee-Won Kang

Chang-soo Park

Avner Dor

Moshe Twitto

Ki-Jun Lee

Myung-Kyu Lee

Man-Keun Seo

Hye-Jeong So

Jae-Yoel Kim

Seung-Jae Lee

Dong-Ku Kang

Young-Hwan Lee

Kyung-jin Kim

Dong-Hwan Lee

Beom-Kyu Shin

Han-woong Yoo

Young-Geon Yoo

Eun-cheol Kim

Ung-hwan Kim

Jaehong Kim

Yoon-Dong Park

Dong-Hyuk Chae

Jae-woong Hyun

Sung-Jae Byun

Yun-Tae Lee

Elona Erez

Ju-hee Park

Si-Hoon Hong

Hee-seok Eun

Se-Jin Lim

Nam-Shik Kim

Dae-Wook Kim

Shay Landis

Min-Goo Kim

Jong-Won Lee

Seung-hoon Lee

Joo-Young Hwang

Hak-soo Yu

Tae-Hwan Kim

Sang-Min Kim

Yaron Shany

Yong-Woo Park

Je-Hyuck Song

Hyoung-Joon Kim

Jong-han Kim

Eran Hof

Jae-Yeol Kim

Dong-Joon Shin

Yoo-cheol Shin

In-Su Choi

Byung-Ho Min

Hyung-June Kim

Sung-Rae Kim

Hyun-Woo Park

Kwang-Hoon Kim

Hak-Sun Kim

Jung-Il Park

Michael Erlihson

Seung-Chan Lim

Young-Jun Hwang

Geun-soo Kim

Sung-Han Choi

Chan-Geu Park

Sung-Han Jung

Geun-Yeong Yu

Kwang-hoon Kim

Bi-woong Chung

Hyun-Seuk Yoo

Chang-kyu Seol

Kwang-gu Lee

Beom-kyu Shin

Ho-sung Park

Dashevsky Shmuel

Sung-chung Park

Sung-Chung Park

Dong-Whan Lee

Jong-Ha Kim

Dong-Sup Jin

Ji-Youp Kim

Seong-Hoon Woo

Soon-Jae Won

Jung-Soo Chung

A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.

Cross-point memory device and method for converting and storing write data and associated parity to achieve uniform bit error rates

A method and system of recovering data includes reading reference codewords, which have code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed. A decoder input of a corrected target codeword is generated based on an operation process using the target codeword and the reference codewords. An ECC decoding process is performed again on the decoder input of the corrected target codeword.

Method of recovering data and memory system and raid storage system using the same

A method of setting a read voltage by a memory controller and a storage device are provided. The method includes controlling a memory device to read data from memory cells by applying a test read voltage to a selected word line; receiving, from the memory device, cell count information corresponding to a read operation of the memory device, and renewing the test read voltage by using the cell count information and a cost function to find an optimum read voltage, the cost function being determined for each read voltage level; and determining a read voltage by performing the controlling of the memory device and the renewing of the test read voltage at least once.

Memory controller, method of operating the same and storage device including the memory controller

Resistive memory device and resistive memory system including a plurality of layers, and method of operating the system

A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.

Memory controller for controlling memory device based on erase state information and method of operating the memory controller

A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Method of decoding low density parity check (LDPC) code, decoder and system performing the same

A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.

Storage devices including logical to physical address mapping and methods of operating

A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key.

Memory device, memory system, and method of operating the memory system

An application specific integrated circuit (ASIC) tangibly encodes a program of instructions executable by the integrated circuit to perform a method for fast Chase decoding of generalized Reed-Solomon (GRS) codes. The method includes using outputs of a syndrome-based hard-decision (HD) algorithm to find an initial Groebner basis G for a solution module of a key equation, upon failure of HD decoding of a GRS codeword received by the ASIC from a communication channel; traversing a tree of error patterns on a plurality of unreliable coordinates to adjoin a next weak coordinate, where vertices of the tree of error patterns correspond to error patterns, and edges connect a parent error pattern to a child error pattern having exactly one additional non-zero value, to find a Groebner basis for each adjoining error location; and outputting an estimated transmitted codeword when a correct error vector has been found.

Groebner-bases approach to fast chase decoding of generalized Reed-Solomon codes

Memory Controller for controlling memory device based on erase state information and method of operating the memory controller

A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

Nonvolatile memory devices and methods of controlling the same

A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.

Memory system and method of operating the memory system

Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.

Method for operating non-volatile memory controller

Growing community of inventors

Yongin-si, South Korea

Jun-Jin Kong