Samsung Electronics Co., Ltd.

Samsung Israel Research Corporation

Samsung Display Co., Ltd.

Jun Jin Kong

Kyoung Lae Cho

Hong Rak Son

Seung-Hwan Song

Jae Hong Kim

Yong June Kim

Sung Chung Park

Dong Hyuk Chae

Eun Chu Oh

Avner Dor

Heeseok Eun

Dong Ku Kang

Yaron Shany

Moshe Twitto

Seung Jae Lee

Jong Han Kim

Jaehong Kim

Dae Seok Byeon

Pilsang Yoon

Sung-Jae Byun

Ji Su Kim

Yoon Dong Park

Pil Sang Yoon

Shay Landis

Amit Berman

Dongku Kang

Seung Hoon Lee

Dae Hyun Kim

Jae-Hong Kim

Dae-Hyun Kim

Daeseok Byeon

Jung Hyun Lee

Jisu Kim

Hongrak Son

Tae Hun Kim

Dong Hwan Lee

Yong Kim

Elona Erez

Young Hwan Lee

Ki Jun Lee

Beom Kyu Shin

Nam Phil Jo

Uri Beitler

Jung Soo Chung

Myung Kyu Lee

Heon Hwa Cheong

Ki-Jun Lee

Myung-Kyu Lee

Chang Kyu Seol

Yoon Sun Park

Seong Hyeog Choi

Se Jin Lim

Shmuel Dashevsky

Yeong Geol Song

Dong Jin Shin

Ji Sang Lee

Eran Hof

Donghun Yu

Michael Erlihson

Dong-Min Shin

Dong Min Shin

Han Woong Yoo

Chan Ho Yoon

Sung-Rae Kim

Dong Hun Yu

Dongsup Jin

Young Hee Lee

Jong Seon No

Yong-Gyu Chu

Jae Hun Jang

Jin-Hoon Jang

Man Keun Seo

Taehyun Song

Changkyu Seol

Sang Hoon Lee

Soojung Ryu

Hong-Rak Son

Yun Tae Lee

Chang Soo Park

Kwang Ho Kim

Eunae Lee

Dong-hoon Yoo

Sang Myeon Han

Evgeny Blaichman

Yesin Ryu

Young Kyoo Kim

Jeongwook Kim

Suk Jin Kim

Kyoung June Min

Jihyun Choi

Hyuck-Sun Kwon

Min Uk Kim

Young Bae Kim

Jae Yoel Kim

Kwanghoon Kim

Kwang Hoon Kim

Hee Seok Eun

Dong Kwan Suh

Moshe Schwartz

Sunggi Ahn

An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.

Error correction code circuits, semiconductor memory devices and memory systems

A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Memory device and memory system including the same

A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Non-volatile memory device, operating method thereof, and storage device having the same

A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ioperation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ioperation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Decoder performing iterative decoding, and storage device using the same

A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Semiconductor memory devices and memory systems including the same

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.

Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Semiconductor memory device, controller, memory system, and operation method thereof

A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

Non-volatile memory device and a read method thereof

A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Method of operating decoder for reducing computational complexity and method of operating data storage device including the decoder

A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.

Data storage system

Growing community of inventors

Yongin-si, South Korea

Jun Jin Kong