Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Jun Iwamura

Tohru Sasaki

Kazuyuki Omote

An integrated standard cell consisting of a plurality of standard cells each having a logical area, at least one power supply line, and one ground line, which further includes two clock signal lines for supplying clock signals. These signals are formed within each standard cell and are provided outside of the power supply line and the ground line, in parallel thereto. The two clock signal lines are connected to the logical area through each shunt line which substantially extends in the vertical direction to the clock signal lines. With this construction, a quantitative prediction for the time delay of clock signals which propagate in the clock signal lines becomes easy, thereby preventing any skew of the clock signals from occurring.

Integrated standard cell including clock lines

An analog to digital converter comprising a data strobe terminal to which a signal is supplied upon the start of the converting operation, a delay circuit having a transistor with controlled conduction resistance and having its gate supplied with an analog input signal, an EX-OR gate having a first input terminal connected to the data strobe terminal and a second input terminal connected to the data strobe terminal through the delay circuit, an AND gate to which the output signal of the EX-OR gate and a clock pulse are supplied, and a counter for counting the output signal of the AND gate, whereby to produce the output of the counter as a digital signal.

Analog to digital converter

A three-output level logic circuit comprises an output stage and a drive stage for driving the output stage. The output stage includes first and second MOS transistors connected in series between first and second power sources and a terminal is provided for producing three-state output signals. The drive stage includes third to sixth MOS transistors connected in series between the first and second power sources. A terminal is provided for supplying a data signal to the fourth and fifth MOS transistors. A control signal is supplied in common to the gate electrodes of the third to sixth MOS transistors. The conductivity types of the first to sixth MOS transistors are selected to operate the logic circuit with one control signal input and one data signal input.

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Yokohama, Japan

Jun Iwamura