Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Jun Inagawa

Yasuhiro Hayashi

Tadashi Kojima

Masahide Nagumo

Hiroshi Kobata

Makoto Kubo

Shiroshi Kanemitsu

Takaaki Kawakami

Kazuhiro Tabuchi

Kunihiko Kodama

Takeshi Inagaki

Toshihiko Kaneshige

Meisei Nishikawa

Hirotoshi Aizawa

Hirotoshi Alzawa

According to one embodiment, an image processing device includes a defect correcting unit, a noise-reduction processing unit, and a selecting unit. The defect correcting unit executes defect correction on a target pixel. The defect correcting unit switches, according to the level of contrast determined concerning a plurality of peripheral pixels, a first correction value obtained through averaging processing for signal values of the peripheral pixels and a second correction value other than the first correction value.

Image processing device and solid-state imaging device including a defect correcting function

According to the Embodiments, an Image Processing apparatus includes a pixel interpolation processing unit. The pixel interpolation processing unit generates a sensitivity level value through addition of a first frequency range component of an image signal for a lacking color component and a second frequency range component of a frequency band lower than the first frequency range component. The pixel interpolation processing unit adjusts a ratio of the first frequency range component to be added to the second frequency range component.

Image processing apparatus and camera module

An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow. Writing information data read from the disc to the buffer memory is performed in response to a reproduction stage clock, and reading from the buffer memory is in response to a signal processing stage clock. The signal processing stage clock for reading information data may be derived from the reproduction stage clock.

Disc data reproducing apparatus and signal processing circuit

An apparatus for reproducing disc data of a compressed image type or another type includes a decompression circuit to decompress the disc data read from the disc in accordance with a reference clock signal. When the disc data is not image type data, the frequency of the reference clock is lowered to reduce power consumption.

An apparatus and a signal processing circuit for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow, and/or to reduce power consumption in a digital-to-analog converter. When the data to be read is ROM data, reading from the buffer memory is conducted in response to a varying frame clock signal, and the frequency of a reference clock signal to the digital-to-analog converter is reduced.

Disc data reproducing apparatus and signal processing circuit for

An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from going overflow/underflow. Writing information data read from the disc to the buffer memory is performed in synchronism with a reproduction stage clock signal, and reading from the buffer memory is in synchronism with a signal processing stage clock. The signal processing stage clock for reading information data from the buffer memory is changed in accordance with the amount of information data stored in the buffer memory for preventing interruptions in data reproduction.

Disc data reproducing apparatus and signal processing unit for

An apparatus for reproducing data stored on a disc in a plurality of tracks connected in a continuous spiral or separated in concentric tracks. The apparatus includes a device for rotating the disc, an optical pickup device aligned with one of the tracks for reading the data from the track, the pickup being subject to jump movement of alignment with the track into alignment with another track in response to movement of the device, a buffer memory device temporarily storing successive portions of the data read from the track for delaying reproduction of the data for a predetermined time after the reading of the data, a track jump detection device for detecting movement of the pickup device into alignment with anothr track and interrupting temporary storage of the data read from the other track by the buffer memory device, a drive device for moving the pickup device with respect to the disc for reading data, and for changing the alignment of the pickup device from the other track to the one track in response to the track jump detection device, and an output device for substantially uninterrupted reproduction of the temporarily stored data.

Erroneous track jump restoration apparatus for optical record disc player

An error correction circuit in which an error location polynomial is determined on the basis of the code word of the code of a double correction BCH symbol in Galois field GF(2.sup.m), thereby determining the error location and error pattern necessary for the error correction. The error correction circuit includes: (a) means for generating a syndrome S.sub.i (i being an integer) from the code word: (b) first and second means for holding S.sub.1 and S.sub.0 out of the syndromes outputted from the syndrome generating means; (c) means for effecting the following calculation on the basis of the syndrome generated by the syndrome generating means:

Error correction circuit

An apparatus divides one element .alpha..sup.i of a Galois field GF(2.sup.m) by another element .alpha..sup.j of the field. Divider data .alpha..sup.j are supplied to one of the first linear shift registers and to the other first linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. Simultaneously, dividend data .alpha..sup.i are supplied to one of the second linear shift registers and to the other second linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. '1' detector circuits are connected to the outputs of the first linear shift registers, respectively. The first linear shift registers and the second linear shift registers are shifted several times until any '1' detector circuit detects '1' in response to output signals from a 2-input AND gate. When '1' is detected, a NOR gate supplies a signal of logical '0' to the AND gate, whereby the AND gate stops supplying output signals. 2-input AND circuits are connected at one input terminal to the outputs of the '1' detector circuits and at the other input terminal to the outputs of the second linear shift registers. The AND circuit connected to the '1' detector circuit supplies the data stored in the second linear shift register to which it is connected. The data representing the quotient of the division .alpha..sup.i -.alpha..sup.j, are delivered through an OR circuit.

Apparatus for dividing the elements of a Galois field

Data representing one element .alpha..sup.i of a Galois field GF(2.sup.m) are stored in a first linear shift register, and data representing another element .alpha..sup.j of the Galois field GF(2.sup.m) are stored in a second linear shift register. 2.sup.m elements of Galois field GF(2.sup.m) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter which includes a decoder and an encoder. The data representing element .alpha..sup.j are supplied from the second linear shift register to the decoder. If the data representing the reciprocal of element .alpha..sup.j are stored in the converter, they are read from the encoder. If they are not stored in the converter, the first linear shift register and the second linear shift register are shifted N times by control pulses generated by a NOR gate and an AND gate until any one of the reciprocal data are read from the encoder, whereby the register supplies data representing .alpha..sup.i+N and the register supplies data representing .alpha..sup.- (j+N). A multiplier multiplies element .alpha..sup.i by reciprocal .alpha..sup.j or multiplies element .alpha..sup.i+N by reciprocal .alpha..sup.-(j+N), thereby performing the division: a.sup.i .div..alpha..sup.j (=.alpha..sup.i-j).

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Kanagawa-ken, Japan

Jun Inagawa