Skhynix Inc.

Korea University Research and Business Foundation

Jun Il Moon

Myeong Jae Park

Byung Kuk Yoon

Ji Hwan Park

Jong Sun Park

Seong Yoon Kang

Disclosed are a bus inversion encoder module that utilizes future data in a data bus including a serializer with minimum latency and high transition reduction efficiency by comparing current data with both past data and the future data and encoding the current data, and a bus inversion system including the same. The bus inversion encoder module uses current data, past data, and future data transmitted through a bus and each including a plurality of bits, determines whether to invert the current data, and generates a current flag and coded current data by using whether to invert, an output flag, and the current data. The output flag is generated by summing the current flag and the coded current data and serially converting the current flag and the coded current data.

Bus inversion encoder module and bus inversion system including the same

In an embodiment of the present disclosure, an integrated circuit includes: a first interface suitable for receiving first to Ndata, where N is an even number equal to or greater than 2, and first to Nmulti-phase clocks; an interface conversion circuit suitable for generating serial data based on the first to Ndata that are received through the first interface, and generating a data strobe signal for strobing the serial data based on the first to Nmulti-phase clocks that are received through the first interface; and a second interface suitable for receiving the serial data and the data strobe signal.

Integrated circuit and memory system

A clock generator circuit includes: first to Nnodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to Nnodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to Nnodes have a first level, and the signals of odd-numbered nodes among the first to Nnodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to Nnodes have the same level.

Clock generator circuit and integrated circuit including the same

A delay circuit includes a first delay line suitable for delaying a first clock by a delay value that is adjusted based on a delay control code; a delay control circuit suitable for comparing a phase of the first clock delayed through the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having, based on a delay control code, a delay value corresponding to a half of the delay value of the first delay line.

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Gyeonggi-do, South Korea

Jun Il Moon