Rohm Co., Ltd.

Jun Iida

Naoki Kurihara

Hiromitsu Kimura

Noboru Takizawa

Koji Nigoriike

Yoshinobu Ichida

Yoshikazu Iinuma

Takashi Nemoto

A data holding device according to the present invention includes a loop structure portion LOOP for holding data using a plurality of logic gates (NANDand NAND) connected in a loop, a nonvolatile storage portion (NVM) for storing in a nonvolatile manner the data held in the loop structure portion (LOOP) by using the hysteresis characteristics of ferroelectric elements, a circuit separating portion (SEP) for electrically separating the loop structure portion (LOOP) and the nonvolatile storage portion (NVM), and a set/reset controller (SRC) for generating a set signal (SNL) and reset signal (RNL) based on data stored in the nonvolatile storage portion (NVM), wherein the plurality of logic gates are each set and reset to an arbitrary output logic level in accordance with the set signal (SNL) and reset signal (RNL).

Data holding device

A delay circuit having a delay element circuit composed of a plurality of series-connected first circuit elements being connected to a common power supply line and having a delay time varying correspondingly to a voltage of the common power supply line, the delay element circuit being adapted to receive an input signal and output an output signal obtained by delaying the input signal, and a PLL circuit including an oscillator circuit composed of a plurality of series-connected second circuit elements, which are equivalent to the first circuit elements, respectively, are connected to the common power supply line. The PLL circuit is adapted to oscillate the oscillator circuit at a predetermined frequency locked to a reference clock frequency by comparing a phase of the reference clock signal with a phase of an output frequency of the oscillator circuit and controlling the voltage of the power supply line according to a result of the comparison.

Delay circuit

A delay time control circuit comprises a delay circuit composed of 2,series-connected unit delay circuits each including a pair of series-connected, first and second inverters, where n is an integer equal to or more than 2, buffer circuits each connected to an output of each of the first and second inverters of the unit delay circuits of the delay circuit, 2,first connection lines each connecting between outputs of adjacent ones of the buffer circuits connected to the second inverters and 2,second connection lines each connecting between adjacent ones of the first connection lines. In response to an input signal input to the first inverter of first one of the unit delay circuit, an output signal delayed with respect to the input signal is obtained through one of the first connection lines and one of the second connection lines.

Delay time control circuit

A multi-channel D/A converter is formed with a plurality of converter units, each having one single input transistor and a plurality of output transistors which together form current mirrors. Mutually corresponding ones of these output transistors of different ones of the converter units, which are switched on and off together, are disposed adjacently and connected together to a trunk power supply line such that the parasitic resistances through the conductive lines connected to the output transistors are alike and the conversion characteristics of the individual converter units also become alike. One common input transistor may be shared by all of the converter units for further improving the conversion characteristic.

Multi-channel digital-to-analog converters comprising with a plurality

A D/A converter has one single input transistor used in common with a plurality of output transistors to together form current mirrors, and a decoder serves to sequentially select the current mirrors in response to a digital input, causing to generate a corresponding analog output from currents from selected ones of the current mirrors. The commonly used input transistor is centrally located with respect to the current mirrors such that the difference between the maximum and minimum distances, or that between the maximum and minimum parasitic resistances, between the input transistor used in common and the output transistors is reduced and the conversion characteristic can be improved.

Digital-to-analog converter with current source centrally located

An active terminator comprises a thermal shutdown circuit. When this circuit detects a predetermined high temperature, this information is supplied to a driver, and the active terminator stops operating. The signal from the thermal shutdown circuit is also supplied to an RS latch circuit that stores information to the effect that the thermal shutdown circuit has detected high temperature, and that the active terminator has stopped operation. A computer examines the contents of this RS latch circuit so that it can be determined that the terminator has stopped operating, and communication errors can therefore be prevented by, for example, reducing the data transfer rate accordingly.

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Kyoto, Japan

Jun Iida