Raytheon Company

Gte Laboratories Incorporated

Jun-ichi Sano

Edward T Lewis

Moshe Mazin

Miles E Goff

Lance A Glasser

Dennis A Henlin

Raymond S Pengelly

James E Meister

M Halberstam

A mixer circuit is provided which incorporates inductive elements for low voltage applications. The circuit consists of a balanced amplifier and a switch composed of transistor pairs driven by a local oscillator signal for multiplying the signal to produce a circuit output signal having a predetermined intermediate frequency. Inductors are used to provide degenerative feedback in the balanced amplifier portion of the circuit. The inductors generate negligible noise and produce a negligible dc voltage drop. The transistors in the circuit are thereby maintained in saturation regions of operation as desired. In accordance with another aspect of the invention, an inductor or, alternatively, a parallel inductor-capacitor circuit, is used as a constant current source in conjunction with the input transistors in the balanced amplifier portion of the circuit.

Low noise mixer circuit having passive inductor elements

A content limit addressable memory (CLAM) having a plurality of lower and upper limits stored therein for comparison to corresponding subfields of an input word. Each corresponding upper and lower limit forms a bracket. Corresponding brackets form a window. The brackets correspond to the subfields and are of the same number of bits. The brackets and subfields are alterable in width to allow each bracket and subfield to have any number of bits in multiples of two. A valid match of the input word with any window can occur with any combination of the brackets of a window matching or not matching the corresponding subfields of the input word. A plurality of outputs corresponding to each of the windows indicates a match of the corresponding window to the input word. Additionally, the CLAM can compare data stored therein against an applied window with the matching operations as described above.

Content limit addressable memory

An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines; a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select one of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.

High density read-only memory

A variable field content addressable memory (VFCAM) unit cell comprises a 4-bit content addressable memory, a programmer and a field selector. A limited capability of comparing between limits is provided by using mask bits at the data line inputs to the VFCAM unit cell. A plurality of VFCAM unit cells may be cascaded vertically and horizontally to provide a Y words by X bits VFCAM array. The VFCAM array is programmable by a field code coupled to field partition logic which selects the same number of fields in all memory locations and the number of bits in each field, and an operational VFCAM system results when the VFCAM array is coupled to an input address decoder, an I/O register and an output encoder.

Variable field content addressable memory

An inverter amplifier employing NMOS FET's having a plurality of capacitance coupled inverter amplifier stages arranged in series. A DC bias is provided at the input of each amplifier stage by a DC bias generator of a reference voltage source, an operational amplifier, and a reference inverter arranged in a negative feedback loop. The DC bias generator is applied to the input of each amplifier stage.

Inverter amplifier

An NMOS FET circuit for charging a storage capacitor to a voltage higher than the power supply voltage. The circuit includes several stages each including a capacitance and FET switches. In response to a high level control signal the FET's in effect connect each capacitance between the supply voltage and ground to charge the capacitances. Then, in response to a low level control signal the FET's in effect connect the capacitances in series between the supply voltage and the storage capacitor thus transferring a portion of the charges in the capacitances into the storage capacitor. The charge placed in the storage capacitor produces a voltage thereacross which is greater than the supply voltage.

Apparatus for charging a capacitor

Circuit for converting input signals at TTL voltage levels to output signals at voltage levels for use with MOS logic circuits. The circuit employs an arrangement of NMOS FET's. Six FET's are arranged in pairs to form three inverters. Another FET is connected in series between the input terminal and different portions of the first and second of the three inverters. The output of the second inverter is fed back to the gate electrode of one of the FET's of the first inverter and to the gate electrode of the series connected FET. The output of the second inverter is also applied to the third inverter. The excursion between voltage levels representing logic 1 and logic 0 at the output of the third inverter is greater than the excursion between voltage levels representing logic 1 and logic 0 at the input to the circuit.

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Chelmsford, MA, United States of America

Jun-ichi Sano