Zaidan Hojin Handotai Kenkyu Shinkokai

Semiconductor Research Foundation

Fuji Photo Film Company, Limited

Olympus Optical Company, Ltd.

Nippon Gakki Seizo Kabushiki Kaisha

Nikon Corporation

Stanley Electric Co., Ltd

Research Development Corporation of Japan

Other

Mitsubishi Denki Kabushiki Kaisha

Agency of Industrial Science and Technology

Jgc Corporation

Tohoku Electric Power Company, Inc.

Research Development Corporation

Toyo Denki Seizo Kabushiki Kaisha

Jun-ichi Nishizawa

Tadahiro Ohmi

Takashige Tamamushi

Masahiro Konishi

Nobuo Takeda

Takashi Yoshida

Sohbe Suzuki

Atsushi Yusa

Mitsuhiro Kimura

Yasuo Okuno

Ikuo Shiota

Ken-ichi Nonaka

Hideo Maeda

Toru Teshima

Hidetoshi Yamada

Terumoto Nonaka

Koji Shimanuki

Toru Kurabayashi

Takashi Mizusaki

Yasunori Mochida

Takashi Kitsuregawa

Keishiro Takahashi

Kenji Yamamoto

Yutaka Hayashi

Seiji Matsumoto

Makoto Murakoshi

Tsutomu Nakamura

Tadahiko Hotta

Ikuo Fujimura

Kaoru Motoya

Junji Ito

Shin Yamashita

Koichi Mitamura

Yoshinobu Ohtsubo

Kentaro Nakamura

Kiyoo Mitsui

Kazuomi Ito

Ken Suto

Nobuaki Manada

Mitsuhiko Dohzono

Toyota Wako

Mitsuo Ikehara

Koji Ishibashi

Yasunori Kishi

Kitsuhiro Kimura

Hiroo Takahashi

Kiyoshi Wagatsuma

Ohmi Tadahiro

Sinpei Maruyama

Bogdan M Wilamowski

Tetsuo Okada

Toshiyuki Kishine

Shinzo Kasai

A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in the current path to accomplish storing. Since the bulk mobility of a semiconductor is far larger than the surface mobility, the transit time of the carriers is much improved. Furthermore, since each structure of the memory cells is formed perpendicular to the semiconductor surface, the surface occupation area per memory cell is reduced. Thus, a high-speed and high-density semiconductor memory device is provided.

High-speed and high-density semiconductor memory

A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Field effect transistor having saturated drain current characteristic

g A field effect transistor has the property that the product of its active total series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of this transistor, the active total series resistance being the sum of the active resistance from source to channel, the active resistance of this channel and the active resistance from channel to drain. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in such fashion in response to a small increase in the reverse gate voltage applied, that no narrow lengthy path is formed between the depletion layers. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Field effect transistor having unsaturated drain current characteristic

A semiconductor device having a source region, a drain region and a channel region which are formed in a surface portion of a semiconductor substrate, and a gate formed with a material having a relatively high built-in voltage relative to the source region. This semiconductor device may further include, in the semiconductor substrate to extend along the channel region, a highly-doped region having a conductivity type opposite to that of the source region. This highly-closed region may have an impurity concentration gradient which is greater toward its portion facing the abovesaid surface of the substrate. These arrangements serve to prevent extinction of memory due to current leakage during absence of bias voltage which otherwise would develop in semiconductor devices having short-channel and thin gate oxide layer, and due to irradiation of alpha-particle onto the device.

Short channel mosfet with buried anti-punch through region

A semiconductor material to be etched is held in a reaction chamber at a predetermined temperature. A reactive etching gas such as a chlorine gas is introduced into the reaction chamber for a first period of time. Thereafter, the reaction chamber is evacuated for a second period of time, and ultraviolet radiation is applied to the semiconductor material for a third period of time within the second period of time for thereby etching the semiconductor material to a depth on the order of a molecular or atomic layer.

Dry etching method

A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus. The metal electrodes and the source electrode are formed by depositing a metal and a low-resistance semiconductor selectively or both in one location within the growing apparatus.

Semiconductor device and method of manufacturing same

A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.

Notched insulation gate static induction transistor integrated circuit

In a method of and an apparatus for epitaxially growing a chemical-compound crystal, a plurality of raw-material gasses are alternately introduced into a closed chamber of a crystal growing device to grow the crystal placed within the closed chamber. At growing of the crystal, a light from a light source is emitted to a crystal growing film of the crystal. Intensity of a light reflected from the crystal growing film and received by a photo detector is measured. Charge amounts of the respective raw-material gasses are controlled by a control system on the basis of a change in the reflected-light intensity, thereby controlling a growing rate of the growing film.

Method of and apparatus for epitaxially growing chemical compound crystal

A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area. An insulating film formed to cover at least a portion of a surface of the fifth semiconductor area and a least a portion of the surface of the second semiconductor area, which is put between the forth semiconductor area and the fifth semiconductor area. An insulated-gate control electrode is formed on the insulating film. The first and third semiconductor areas serve as a first and second main electrode areas, respectively.

Insulated gate control static induction thyristor

Short channel MOSFET with buried anti-punch through region

In a MOS controlled power device, or MOS composite a static induction thyristor, an static induction thyristor (SI thyristor) unit, a MOS transistor connected in cascode relation to the SI thyristor unit and a voltage regulation element are merged onto the single monolithic chip. The SI thyristor unit has a cathode region of first conductivity type having high impurity concentration, an anode and a gate regions of second conductivity type having high impurity concentration, and a channel region of first conductivity type having low impurity concentration. The MOS transistor has a drain region which is the same region as the cathode region, a well or a base of second conductivity type formed adjacent to the channel region of the SI thyristor unit, and a source region of first conductivity type having high impurity concentration. The source region is formed within the well or above the base. The voltage regulation element comprises a first semiconductor region of second conductivity type, and a second semiconductor region of first conductivity type, both having high impurity concentration.

MOS composite static induction thyristor

A static induction device (SI device) at least shares a structure in which an SI thyristor, an IGT and a capacitor are merged onto the single monolithic chip. The SI thyristor has a cathode, an anode and a gate regions, and a channel. The IGT has a well on a surface of the channel, a source and drain regions within the well, a gate insulating film on the well, and a gate electrode on the gate insulating film. The capacitor comprises the gate region of the SI thyristor, the gate insulating film on the gate region, and the gate electrode. The cathode and the drain region are connected to each other through a high-conductive electrode.

Static induction device

A semiconductor device comprises a vertical MIS-SIT which has a smaller source-to-drain distance for operation at ultra-high speed. The semiconductor device has a substrate crystal for epitaxial growth thereon, least two semiconductor regions of different conductivity types deposited by way of epitaxial growth on the substrate crystal according to either metal organic chemical vapor deposition (MO-CVD) or molecular layer epitaxy (MLE), thereby providing a source-drain structure, a gate side formed by etching the semiconductor regions of the source-drain structure, the gate side comprising either a (111)A face or a (111)B face, and a semiconductor region deposited as a gate by way of epitaxial growth on the gate side according to either MO-CVD or MLE.

Method of manufacturing a static induction field-effect transistor

In an apparatus for growing a GaAs single crystal from its melt, As vapor which is controlled appropriately of its pressure is applied from an As chamber to the surface of the GaAs melt in a vessel throughout the growing process through an As passage communicating between the melt vessel and the As chamber, while establishing a gentle temperature gradient in the passage leading from the GaAs melt vessel to the As chamber. Whereby, a GaAs single crystal having a large diameter and a good crystal perfection with minimized deviation from stoichiometry and minimized lattice dislocation can be obtained.

Apparatus for growing a GaAs single crystal by pulling from GaAs melt

Growing community of inventors

Sendai, Japan

Jun-ichi Nishizawa