Fujitsu Corporation

Jun-ichi Mogi

Kiyoshi Miyasaka

Fumio Baba

Seiji Enomoto

Shigeki Nozaki

Tsutomu Mezawa

Takashi Yabu

A semiconductor circuit consisting of a dynamic-type circuit and a bias-voltage generating circuit. The bias-voltage generating circuit is comprised of a first bias-voltage generator and a second bias-voltage generator. The first generator absorbs a variable substrate current, the magnitude of which is proportional to the operating frequency of the dynamic-type circuit, while the second generator absorbs a substrate current, the magnitude of which is not proportional to the operating frequency of the dynamic-type circuit. Alternately, both portions of the substrate current may be absorbed via the same circuitry.

Semiconductor substrate bias circuit

A lower member of a cross wire structure formed in a semiconductor device, such as an MIS type semiconductor memory device, is provided with a structure of at least two layers of an impurity-containing polycrystalline semiconductor material according to the method disclosed. These layers are connected in parallel and their resistance is thus decreased. Furthermore, since these layers may be formed within insulating films over a semiconductor substrate, the degree of integration of the semiconductor device may be enhanced. The method for producing the cross electrodes allows simultaneous fabrication of other semiconductor devices, for instance MIS devices with components commonly fabricated with the cross electrode structures.

Semiconductor device having cross wires

Disclosed is the addition of a capacitor circuit for augumenting the voltages at predetermined points in a sense amplifying circuit, in order to ensure a satisfactory refreshing of memory cells, since, if the potentials at the connecting points between a sense amplifying circuit and bit lines fall below a predetermined value when the sense amplifying circuit is caused to operate, it is difficult to achieve a complete refreshing of the memory cells.

Memory circuit

Self-aligned IGFET structure having a source region, a drain region and a gate electrode placed between the source and drain regions to define a channel region. The gate electrode is provided with an extended end portion on a relatively thick field oxide layer and having a length no less than a predetermined channel length on one side of the channel region so that the breakdown voltage is not decreased on that one side of the channel region.

Growing community of inventors

Kawasaki, Japan

Jun-ichi Mogi