Samsung Electronics Co., Ltd.

Lg Innotek Co., Ltd.

Lg Hausys, Ltd.

Jun Hyoung Kim

Kwang Soo Kim

Geun Won Lim

Seok Cheon Baek

Young-Jin Kwon

Si Wan Kim

Kyoung Taek Oh

KiTae Kim

Bong Hyun Choi

Jae Bong Hwang

Eun Sik Nam

A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

Vertical memory device

A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Method of fabricating a semiconductor memory device including an extension gate cutting region

Semiconductor device including a cell array region and an extension region

The present invention relates to an apparatus for manufacturing artificial leather, the apparatus including an embossing molding device capable of efficiently forming an embossed pattern on the surface of artificial leather through vacuum adsorption molding and a method of manufacturing artificial leather using the apparatus.

Apparatus for manufacturing artificial leather and method of manufacturing artificial leather using the same

A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

A three-dimensional semiconductor memory device includes first and second gate stacked structures, disposed on a base substrate, and stacked in a direction perpendicular to a surface of the base plate, the first and second gate stacked structures including gate electrodes spaced apart from each other and stacked; a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures; and vertical channel structures passing through the first and second gate stacked structures, wherein the first gate stacked structure has first contact pads adjacent to the through region and arranged in a stepped shape, the second gate stacked structure having second contact pads adjacent to the through region and arranged in a stepped shape, at least a portion of the second contact pads overlap the first contact pads on one side of the through region.

Three-dimensional semiconductor memory device

A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.

Vertical memory devices

A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region.

Three-dimensional semiconductor memory device including a penetration region passing through a gate electrode

A light emitting device package is disclosed. The light emitting device package includes a package body, at least one light emitting diode disposed on the package body, a molding layer surrounding the light emitting diode, and a phosphor layer provided on the package body, wherein the phosphor layer extends upward from surface of the package body.

Light emitting device package and light emitting module

A light emitting device according to the embodiment includes a substrate; a buffer layer over the substrate; an electrode including a perforation pattern through top and bottom surfaces of the electrode over the buffer layer; a first semiconductor layer over the electrode; an active layer over the first semiconductor layer; and a second semiconductor layer over the active layer. The first semiconductor layer extends onto a top surface of the perforation pattern by passing through the perforation pattern while making contact with the buffer layer.

Growing community of inventors

Seoul, South Korea

Jun Hyoung Kim