Skhynix Inc.

Jun Ho Lee

Sun Ki Cho

Boo Ho Jung

Yang Hee Kim

Hyun Seok Kim

Young Won Kim

Tae Yong Lee

Sung Woo Han

Ic Su Oh

Bo Hyun Choi

There are provided a storage device and an operating method thereof. A memory controller includes: an operation mode controller for adjusting a standby entry time by using a host idle interval as an interval between host busy periods and a reference interval, and determining an operation mode, based on the adjusted standby entry time and a subsequent host idle interval; and an operation controller for controlling a memory device according to the operation mode.

Storage device and operating method thereof

Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.

Method for reducing output data noise of semiconductor apparatus and semiconductor apparatus implementing the same

Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Provided is an MCP including a plurality chips stacked therein. Each of the chips includes a plurality of inductor pads configured to transmit power or signals, and at both sides of a reference inductor pad, a first and a second inductor pads are formed to generate magnetic fluxes in different directions from each other.

Multi-chip package with improved signal transmission

An electromagnetic interference (EMI) shielding circuit and a semiconductor integrated circuit including the same are provided. The EMI shielding circuit includes a data level comparison unit, a control signal generation unit, and a driver for EMI cancellation. The data level comparison unit generates a data comparison signal by comparing a number of high-level data transmitted through a plurality of data lines and a number of low-level data transmitted through the plurality of data lines. The control signal generation unit generates a driving control signal in response to the data comparison signal. The driver for EMI cancellation outputs an EMI cancellation signal in response to the driving control signal.

EMI shielding circuit and semiconductor integrated circuit including the same

A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.

Semiconductor memory apparatus with power-meshed structure

A semiconductor integrated circuit includes a first voltage line to which a first ground voltage is applied, a second voltage line to which a second ground voltage is applied, a third voltage line to which a first power supply voltage is applied, and a coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line.

Growing community of inventors

Icheon-si, South Korea

Jun Ho Lee