Samsung Electronics Co., Ltd.

Jun-Ho Huh

Je-Kook Kim

Sang-hoon Moon

June-Hee Lee

Sang-Heon Lee

Kwan-Yeob Chae

In-Tae Kang

Sang-Hune Park

Ho-Rang Jang

Seok-Chan Kim

Jae-Chol Lee

Hyung-Kweon Lee

Chae-Hag Yi

Kee-Moon Chun

Hae-Chul Lee

Sang-Ho Seo

Hyung-kweon Lee

A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Modem and RF chips, application processor including the same and operating method thereof

An apparatus, method, chipset, and non-transitory computer-readable storage medium for controlling power are provided. The apparatus includes a receiver configured to receive a data frame and first information related to a next data frame of the data frame; and a controller configured to determine an operation mode as an active mode or a sleep mode based on destination address information of the next data frame and duration information indicating a time during which transmission of the next data frame occurs, wherein the destination address information and the duration information are included in the first information.

Apparatus and method for controlling power

Methods and apparatuses are provided for driving a modem. A Channel Impulse Response (CIR) is computed through channel estimation. An estimation time position is estimated by applying a weighted-average method to the CIR. A time offset is measured by comparing the estimation time position with a reference time position. The time offset is compensated for.

Modem and driving method thereof

An apparatus for and a method of detecting a wobble signal in accordance with a time shift includes comparing a basic wobble signal with reference levels to detect pulses representing the time shift in an analog fashion, and digitally determining a code value for the basic wobble signal on the basis of the widths of the pulses using a channel clock signal and a wobble clock signal. The determined code value is accumulated and serves as a basis on which final wobble data is produced.

Apparatus for and method of detecting a wobble signal in accordance with a time shift

An automatic gain controller includes a voltage control gain amplifier amplifying input signals in response to a control voltage and producing output signals. A level detector detects peak and bottom levels of the output signals of the voltage control gain amplifier, and an analog-digital converter (ADC) converts the detected peak and bottom levels into digital signals. A peak detector detects a digital peak in response to a difference between the digital peak level and digital bottom level, and a voltage controller compares the digital peak and a reference voltage, and controls the control voltage.

Automatic gain controllers and methods for controlling voltage of control gain amplifiers

An apparatus and method for digitally detecting a tracking error signal using multiple phase clocks. The apparatus includes a phase extractor receiving four divided outputs in response to light reflected from an optical disk and extracting four divided phases, respectively, a phase difference detector detecting phase differences between two phases among the four divided phases, a multiple phase clock generator generating a plurality of phase clocks in response to a predetermined clock signal, a phase error detector counting phase differences in response to each of the plurality of phase clocks, summing the counted phase differences, and detecting a phase error, and a tracking error output unit detecting the tracking error signal in response to the phase error and outputting the detected tracking error signal.

Apparatus and method for detecting tracking error signal using multiple phase clocks

A focus layer jump control circuit may include a signal processing block that converts an analog focus error (FE) signal into a digital FE signal, in response to the analog FE signal and a FE selection signal; a layer jump control block that outputs a second control signal, in response to the digital FE signal and a reference clock signal; a focus main filter block that outputs first and second compensation signals that amplify the digital FE signal and that compensate for a phase of the digital FE signal, in response to an internal selection signal; an exponent signal generator that generates an exponent signal, in response to a focus layer jump indicating signal and a first control signal; and an output circuit that outputs a first-order difference signal using the exponent signal, the first compensation signal, and the second compensation signal, in response to the second control signal.

Focus layer jump control circuits and methods of controlling focus layer jumps used by the same

An analog level meter and a method of measuring an analog signal level may be provided. The analog level meter may include a comparator, a duty counter, an analog level detector and/or a digital to analog converter (DAC). The comparator may compare a voltage level of the analog signal with a reference voltage and generate an up-down signal. The duty counter may count a duty value of the up-down signal. The analog level detector may output a duty error value obtained by subtracting a target duty value from the duty value of the up-down signal. The analog level meter may output the reference voltage as a measured value of the analog signal when the duty error value is a desired or predetermined value.

Analog level meter and method of measuring analog signal level

A clock recovery circuit and method for an MPEG-2 system decoder. The clock recovery circuit comprises a digital signal processor including a controller, a PCR/SCR detector, an adder/subtracter unit, a digital filter and a register, a DAC, a low pass filter, a voltage controlled oscillator and a counter. The counter generates a clock value of a desired number of bits. The PCR/SCR detector receives a transport or program stream and detects a PCR or SCR therefrom. The controller checks whether the detected PCR or SCR is an initial value. If the detected PCR or SCR is the initial value, the adder/subtracter unit subtracts the clock value from the counter from the detected PCR or SCR starting from the least significant bit to generate a first value. If the detected PCR or SCR is not the initial value, the adder/subtracter unit subtracts lower-order bit values of the first value corresponding to the desired number from lower-order bit values of the detected PCR or SCR corresponding to the desired number and subtracts the clock value from the counter from the subtracted result to generate a second value. Then, the adder/subtracter unit transfers the second value to the DAC. Also, the adder/subtracter unit adds the clock value from the counter to the first value starting from the least significant bit to generate a system time clock.

Clock recovery circuit and method for MPEG-2 system decoder

A method of reducing a channel hopping time in an MPEG-2 system decoder which can improve the performance of a receiver by minimizing the response time in the event of changing the receiving channel. According to the method, a predetermined storage region is provided in a DRAM, and packet identifier (PID) values of audio and video signals of each program are stored in the storage region. Thereafter, if a receiving channel is changed, the channel-changing operation is performed using the PID values of the audio and video signals stored in the storage region, and thus the time required for the channel change is shortened, thereby reducing the channel hopping time.

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Yongin-si, South Korea

Jun-Ho Huh