Skhynix Inc.

Snu Rdb Foundation

Jun Ho Cheon

Seok Joon Kang

Chang Yong Ahn

Moo Hui Park

Yoon Jae Shin

Young June Park

In Soo Lee

Jeong Ho Yi

Sung Min Seo

A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Nonvolatile memory apparatus for mitigating read disturbance and system using the same

A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Voltage generating circuit and a nonvolatile memory apparatus using the voltage generating circuit

A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Nonvolatile memory apparatus for performing a read operation and a method of operating the same

A non-volatile memory apparatus may include a program current generation circuit, a clamping circuit and a voltage generation circuit. The program current generation circuit may increase a program current based on a memory cell current flowing through a memory cell. The clamping circuit may clamp the memory cell current. The voltage generation circuit may apply a voltage corresponding to a verification-write voltage to the memory cell. Therefore, the verification-write operation may be performed to the memory cell.

Nonvolatile memory apparatus and verification write method thereof for reducing program time

A phase change memory device may include a plurality of word lines, a plurality of bit lines, a phase change memory cell, and a discharging circuit. The word lines and the bit lines may intersect each other. The phase change memory cell may be positioned at an intersection point between the word lines and the bit lines. The discharging circuit may be configured to apply a ground voltage to a non-selected word line adjacent to a selected word line or a non-selected bit line adjacent to a selected bit line.

Phase change memory device capable of decreasing a disturbance

A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.

Semiconductor memory apparatus and operating method

A resistance variable memory apparatus may include a memory cell array and a controller. The memory cell array may include a plurality of resistance variable memory cells. The controller may control a current path flowing through any one memory cell and a current path flowing through the other memory cell to be formed differently from each other in response to at least two address signals.

Resistance variable memory apparatus and operating method thereof

An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. The main analog capacitor may be formed over a semiconductor substrate. The interlayer insulating layer may be interposed between the semiconductor substrate and the main analog capacitor. The plurality of stacked sub analog capacitors may be inserted into the interlayer insulating layer.

Analog capacitor

A resistive memory device includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal and selecting the resistive memory cells, a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array, a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder and a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation in response to a write command and a plurality of write data.

Resistive memory device, operating method thereof, and system having the same

A digital to analog converter may include a reference voltage generation unit that generates a reference voltage and a plurality of unit conversion units connected through an output node. The plurality of unit conversion units may set a voltage level of the output node in response to digital codes and the reference voltage.

Digital to analog converter

A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.

Write driver, variable resistance memory apparatus including the same, and operation method

Embodiments feature a sensor including a nanostructure and methods for manufacturing the same. In some embodiments, a sensor includes a substrate, a first electrode disposed on the substrate, and a second electrode disposed on the substrate. The second electrode is spaced apart from the first electrode and surrounding the first electrode. The sensor includes at least one nanostructure contacting the first electrode and the second electrode, in which the nanostructure is configured to vary an electrical characteristic according to an object to be sensed.

Growing community of inventors

Icheon-si, South Korea

Jun Ho Cheon