Samsung Electronics Co., Ltd.

Jun-haeng Lee

Kwang-il Park

Seung-ju Kim

Tae-ho Lee

In Huh

Youn-sik Park

Hyo-jin Choi

Chang-wook Jeong

Joon-wan Chai

Jeong-hoon Ko

Young-min Oh

Hyun-sun Park

A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system

A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

Growing community of inventors

Hwaseong-si, South Korea

Jun-haeng Lee