Samsung Electronics Co., Ltd.

Jun-gu Kang

Young-mok Kim

Woon-bae Kim

Dae-cheol Seong

Yune-seok Chung

Dong-Il Park

Yongsang Jeong

Seung-hee Go

Min-Hee Uh

Sung-min Kang

Byungeun Yun

Chulho Chung

Myoungkyu Park

A method for forming a semiconductor device includes: providing a substrate including a first and second region; forming a first gate dielectric pattern and a first gate electrode on the first region; forming a second gate dielectric pattern and a second gate electrode on the second region; forming an interlayer dielectric layer on the substrate; forming first source/drain contact holes penetrating the interlayer dielectric layer on the first region; and forming second source/drain contact holes penetrating the interlayer dielectric layer on the second region. A thickness of the second gate dielectric pattern is greater than a thickness of the first gate dielectric pattern. A height of each of the second source/drain contact holes is greater than a height of each of the first source/drain contact holes. A width of each of the second source/drain contact holes is greater than a width of each of the first source/drain contact holes.

Method of fabricating a semiconductor device including source/drain contacts having different heights and different widths

An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

Integrated circuit chip, integrated circuit package and display apparatus including the integrated circuit chip

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Integrated circuit chip, method of manufacturing the integrated circuit chip, and integrated circuit package and display apparatus including the integrated circuit chip

An integrated circuit chip includes a circuit structure, a grounding structure, a bonding layer between the circuit structure and the grounding structure. The circuit structure includes a first substrate, an FEOL structure, and a BEOL structure. The grounding structure includes a second substrate and a grounding conductive layer. The integrated circuit chip includes a first penetrating electrode portion connected to the grounding conductive layer based on extending through the first substrate, the FEOL structure, the BEOL structure, and the bonding layer such that the first penetrating electrode portion is isolated from direct contact with the integrated circuit portion in a horizontal direction extending parallel to an active surface of the first substrate. An integrated circuit package and a display device each include the integrated circuit chip.

Integrated circuit chips, integrated circuit packages including the integrated circuit chips, and display apparatuses including the integrated circuit chips

A semiconductor device includes: a substrate including a first region and a second region; a first gate stack on the first region of the substrate; a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate; a second gate stack on the second region of the substrate; and a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate, wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and wherein a width of the second source/drain contact is greater than a width of the first source/drain contact.

Semiconductor device including contacts having different heights and different widths

Provided are a semiconductor device and a method of forming the same. The semiconductor device includes an active region defined by an isolation layer. A source region portion, a drain region portion and a channel region are located in the active region. The channel region includes a first portion located close to the source region portion and a second portion having a higher threshold voltage than the first portion.

Growing community of inventors

Hwaseong-si, South Korea

Jun-gu Kang