Hynix Semiconductor Inc.

Skhynix Inc.

Soongsil University

Jun-Gi Choi

Yoon-Jae Shin

Hwang Hur

Tae-Kyun Kim

Yong-Kyu Kim

Sang-Jin Byeon

Jae-Il Kim

Hi-Hyun Han

Chang-Hyun Lee

Chang-Kun Park

Jong-Chern Lee

Tae-Yun Kim

Jin-Ho Yoo

Suk-Hyeon Yoon

Hyung-Jun Cho

Hee-Seong Kim

Hyung-Dong Lee

Kwi-Dong Kim

Jin-Hee Cho

Seung-Min Oh

Sang-Hee Kang

Jong-Sam Kim

Sang-hoon Shin

Min-Su Park

Youk-Hee Kim

A wireless power transmission/reception system includes a wireless power transmission circuit and a wireless power reception circuit. The wireless power transmission circuit includes an oscillator, a DC-AC converter that converts a direct current to an alternating current and is turned on/off in response to a control signal, a power transmission coil that transmits AC power, a signal reception coil, and a signal receiver that transfers the control signal to the DC-AC converter. The wireless power reception circuit includes a power reception coil, a rectifier that converts an alternating current to a direct current and is turned on or off in response to the control signal, an control signal generator that generates the control signal, a signal transmission coil, and a signal transmitter that transmits the control signal through the signal transmission coil.

Wireless power transmission circuit

A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a pass or a fail.

Memory device and operating method thereof

A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.

A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

Comparing twice-read memory cell data for error detection in a memory device

A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.

Memory device and method of refreshing the same

A semiconductor device may include: a first latch configured to store data outputted from a memory cell during a first operation; and a fail detection circuit configured to detect a fail by comparing the data outputted from the memory cell to the data stored in the first latch through a second operation performed at a predetermined time after the first operation.

Semiconductor device and operating method thereof

Wireless transceiver circuit with reduced area

A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Semiconductor chip and semiconductor wafer

A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Semiconductor integrated circuit and method for fabricating the same

A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.

Fuse circuit and memory device including the same

A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

Apparatus for supplying voltage free noise and method of operation the same

Apparatus for supplying voltage free from noise and method of operation the same

A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.

Growing community of inventors

Gyeonggi-do, South Korea

Jun-Gi Choi