Fujitsu Corporation

Jun Funaki

Hirohide Sugahara

Akira Kabemoto

Hajime Takahashi

Koji Suzuki

Toshiyuki Shimizu

Koji Hosoe

Takatsugu Sasaki

Michio Numata

Toshihide Tsuzuki

Shoji Tenma

Shoji Temma

Nobuhisa Hattori

An initial value generation circuit generates an initial value taking into consideration the a time delay when a signal is transmitted through the signal wires between a pilot device and other devices, and a processing delay caused in respective devices. When a device receives a system synchronizing signal form another device, the device sets an initial value in a counter. Thereby, the counter value of a counter in a pilot device and counter values of counters in the other devices are made to coincide with each other.

Timing synchronizing system, devices used in the system, and timing synchronizing method

A multiprocessor system having the capability of increasing the speed of a bus clock while retaining high reliability and fault tolerant performance as well as utilizing the current operating system resources. The multiprocessor system is made up of a plurality of processor modules connected together through a duplicated system bus. The duplicated system bus is divided into a plurality of segments, and these segments are coupled together by at least one bus extender mechanism. The multiprocessor system is also provided with first notification means which is provided between bus control mechanisms for controlling the states of physical buses and the bus extender mechanism, and the bus control mechanisms and the bus extender mechanism are mutually notified of the state of each mechanism through the first notification means.

Multiprocessor system connected by a duplicated system bus having a bus

In the case where a CPU executes a write instruction of a control program for a memory mapped register of an external memory, a write address and write data are written into an output buffer, thereby completing the write instruction. Prior to executing a read instruction subsequent to the write instruction, the write address and the write data of the output buffer are transferred to a sync buffer and are stored into a write address holding register and a write data holding register. Further, a using state display register is set into the holding state. When the CPU executes the read instruction, the write data of the write data holding register is written into the memory mapped register and the end of the writing operation is synchronized with the end of the read instruction. When the sync buffer unit receives an interruption instruction in the holding state, an interruption return instruction address is returned to an address of the write instruction of the data in the holding state. The process is restarted from the write instruction of the memory mapped register by the control program by the end of the interruption.

Processor apparatus and its control method for controlling a processor

An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

Asynchronous access system controlling processing modules making

An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second connection unit which connects to the system bus. The first connection unit within the processing module makes a block read request to the shared memory module via the system bus when the first connection unit recognizes a read from the shared memory module requested from the central processing unit. The first connection unit within the processing module comprises an internal bus, an internal buffer storing data read from the shared memory module, a system bus control circuit coupled to the system bus, an internal bus control circuit coupled to the central processing unit via the internal bus, and an internal buffer control circuit controlling write/read of the internal buffer based on a signal from the internal bus control circuit. One of the internal buffer control circuit and the internal bus control circuit invalidates a content of the internal buffer when one of a plurality of invalidating conditions is satisfied.

Asynchronous access system having an internal buffer control circuit

In an asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and at least one shared memory module connected to the system bus, each of the processor modules includes a processor and an internal buffer. The processor writes data into the internal buffer, and the data is read from the internal buffer and is written into the shared memory via the system bus. The asynchronous access system includes a first unit, provided in each of the processor modules, for detecting a predetermined situation regarding a data write from the processor to the shared memory, and a second unit, provided in each of the processor modules, for causing the data stored in the internal buffer to be written into the shared memory module when the first unit detects the predetermined situation.

Asynchronous access system for multiprocessor system and processor

A commercially available clock IC which is easily influenced by a temperature change or the like is used as it is, thereby easily allowing the clock IC to function as a high precision clock IC. A high precision oscillator is provided separately from a clock circuit as a clock IC. On the basis of a clock signal from the high precision oscillator, a predetermined time, for example, one minute is measured by a high precision clock control circuit. A correction signal is transmitted to the clock circuit as a clock IC from a high precision control circuit every measurement of such a predetermined time, thereby allowing the correcting operation of the time information to be executed. The clock circuit is, consequently, made operative at a precision of the high precision oscillating circuit.

Growing community of inventors

Kawasaki, Japan

Jun Funaki