Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi High-tech Corporation

Hitachi Device Engineering Co., Ltd.

Other

Elpida Memory, Inc.

Hitachi Ulsi Engineering Corp.

Hitachi Vsli Engineering Corp.

Vlsi Engineering Corporation

Hitachi, Ltd., Hitachi Vlsi Engineering Corporation

Jun Etoh

Masashi Horiguchi

Kiyoo Itoh

Masakazu Aoki

Ryoichi Hori

Kazuyuki Miyazawa

Kazuhiko Kajigaya

Kazuyoshi Oshima

Manabu Tsunozaki

Akira Endo

Takashi Yamazaki

Yuji Sakai

Hiroshi Yoshioka

Yasunori Yamaguchi

Tetsurou Matsumoto

Makoto Morino

Yasuhiro Kasama

Shinji Udo

Shinichi Ikenaga

Eiji Miyamoto

Mitsuhiro Takano

Sinichi Miyatake

Jiro Sawada

Hirokazu Saito

Atsushi Kumata

Yoshinobu Nakagome

Hitoshi Tanaka

Katsutaka Kimura

Katsuhiro Shimohigashi

Yoshiki Kawajiri

Shin'ichi Ikenaga

Takaaki Noda

Norio Miyake

Eiji Kume

Takeshi Sakata

Kan Takeuchi

Katsumi Matsuno

Koji Kawamoto

Tsugio Takahashi

Takesada Akiba

Isao Yoshida

Toshiaki Masuhara

Osamu Minato

Shuichi Nakagawa

Hiroaki Nambu

Kazuo Kanetani

Noriyuki Homma

Hiroo Masuda

Hiroshi Kawamoto

Tetsuji Kawahara

Hironori Ogawa

Kunihiko Yamaguchi

Youji Idei

Masaaki Nakai

Tetsu Udagawa

Yoichiro Suzuki

Kenichi Ohhata

Terunobu Funatsu

Kyoko Ishii

Shigeki Ueda

Yoshiaki Sakurai

Manabu Ochi

Kenshiro Sakata

Shin Ichi Ikenaga

An object of the present invention is to provide a camera holding device for an automatic analysis apparatus, capable of easily adjusting tip positions of pipetting nozzles having different lengths, even with the use of a single single-focus camera. Therefore, the present invention is a camera holding device for an automatic analysis apparatus, which holds a camera to capture an image of the tip of a pipetting nozzle of the automatic analysis apparatus on a pipetting arm that moves the pipetting nozzle through rotational movement, the camera holding device including: an expansion/contraction part that expands and contracts in a vertical direction with respect to the pipetting arm; an arm-side fixing part that fixes one end of the expansion/contraction part to the pipetting arm; and a camera-side fixing part that fixes the camera to the other end of the expansion/contraction part.

Camera holding device for automatic analysis apparatus

A vibration damping system for a charged particle beam apparatus according to the present invention includes a column through which a charged particle beam passes, a vibration detection unit that detects vibration of the column, a damping mechanism that applies vibration to the column to suppress the vibration of the column, and a control device that controls the damping mechanism. The control device includes a damping gain control unit that amplifies a detection signal of the vibration detection unit with a set amplification factor and outputs an amplified detection signal as a control signal to the damping mechanism, and a saturation suppression unit that adjusts a feedback gain value of the damping gain control unit according to a detection signal of the vibration detection unit, a signal of the damping mechanism, and a maximum output value and a minimum output value of the damping mechanism.

Vibration damping system for charged particle beam apparatus

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

Large scale integrated circuit with sense amplifier circuits for low voltage operation

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

Method for manufacturing memory device provided with a defect recovery mechanism featuring a redundancy circuit

A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

Semiconductor device having redundancy circuit

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory such as a dynamic random access memory (DRAM), having a memory array which is divided into memory mats and a storage capacity of 16 M bits or more, features a defect recovery scheme through employing a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes a comparing circuit having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. In accordance with this, each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected

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Hachioji, Japan

Jun Etoh