International Business Machines Corporation

Ricoh Company, Ltd.

Jun Doi

Keisuke Inoue

Norifumi Ito

Yasushi Negishi

Fumio Kawamura

Hiroshi Horii

Michiaki Tatsubori

Atsushi Yamada

Kaori Fujiwara

Yuji Takahashi

Kiyokuni Kawachiya

Yoshiyuki Namizuka

Takeo Yoshizawa

Hiroshi Hosaka

Yasuo Kawada

Mitsuhisa Kanaya

Masayoshi Miyamoto

Taro Sekiyama

Haruki Imai

Tetsuya Kawaguchi

Christopher James Wood

Hitomi Chiba

Tomonori Fukui

Toshiki Yamashita

Hiroshi Soga

Atsuhshi Yamada

Keiichiroh Katoh

Jyouji Katoh

Techniques for circuit serialization for parameterized-circuit simulation are described. In one example, a system is provided that comprises a processor that executes computer executable components stored in memory. The computer executable components comprise a determination component that determines a first path of computational nodes and a second path of computational nodes of a parameter tree comprising a plurality of computational nodes, wherein the first path of computational nodes and the second path of computational nodes share one or more computational nodes at the beginning of the first path of computational nodes and the second path of computational nodes. The computer executable components further comprise a serialization component that creates a serialized path of computational nodes from the first path of computational nodes and the second path of computational nodes.

Circuit serialization for parameterized circuit simulation

Systems, computer-implemented methods, and computer program products to facilitate batched quantum circuits simulation on a graphics processing unit are provided. According to an embodiment, a system can comprise a first processor that executes computer executable components stored in memory. The computer executable components can comprise a generalization component that generates a first defined matrix representation of a qubit gate and that employs a control mask to generate a second defined matrix representation of a multi-qubit gate. The computer executable components can further comprise an execution component that executes a kernel overhead operation using the first defined matrix representation and the second defined matrix representation to generate a batched kernel.

Batched quantum circuits simulation on a graphics processing unit

A computer-implemented method performed by one or more computing nodes for simulating a gate operation of quantum computing is disclosed. In the method, a problem having 2size is divided into a plurality of sub-problems, each of which has 2size. A first index table for storing a first identifier is prepared for each sub-problem. In response to a request for a gate operation involving exchanges of quantum amplitudes that are designated by a target qubit at least in part, a determination is made as to whether a first condition regarding at least the target qubit and m is satisfied or not. In response to the first condition being satisfied, corresponding first identifiers in the first index table are swapped in place of the exchanges of the quantum amplitudes.

Avoiding data exchange in gate operation for quantum computing gates on a chip

Techniques for simulating a quantum circuit based on fusion of at least a portion of a measure gate is provided. Data representing a quantum circuit comprising a quantum gate and a measure gate is received. The measure gate in the quantum circuit is divided into one or more virtual gates and at least one of the one or more virtual gates is fused with the quantum gate. The gate fusion combines the operations of the fused gates and cache blocking to more efficiently simulate the quantum circuit. In one embodiment, the simulation of the quantum circuit is executed locally on a computing device. Alternatively, the simulation of the quantum circuit is performed remotely over a network via an application program interface ('API') and results of the simulation are reported via the API.

Gate fusion for measure in quantum computing simulation

A computer-implemented method, computer program product, and apparatus are provided. The method includes substituting N&#xd7;N first integer elements, among a plurality of first integer elements obtained by dividing first integer data expressing a first integer in a first digit direction, into a first matrix having N rows and N columns. The method further includes substituting each of one or more second integer elements, among a plurality of second integer elements obtained by dividing second integer data expressing a second integer in a second digit direction, into at least one matrix element of a second matrix having N rows and N columns. The method also includes calculating a third matrix that is a product of the first matrix and the second matrix. The method includes outputting each matrix element of the third matrix as a partial product in a calculation of a product of the first integer and the second integer.

Multiple precision integer multiplier by matrix-matrix multiplications using 16-bit floating point multiplier

A method is provided for reducing consumption of a memory in a propagation process for a neural network (NN) having fixed structures for computation order and node data dependency. The memory includes memory segments for allocating to nodes. The method collects, in a NN training iteration, information for each node relating to an allocation, size, and lifetime thereof. The method chooses, responsive to the information, a first node having a maximum memory size relative to remaining nodes, and a second node non-overlapped with the first node lifetime. The method chooses another node non-overlapped with the first node lifetime, responsive to a sum of memory sizes of the second node and the other node not exceeding a first node memory size. The method reallocates a memory segment allocated to the first node to the second node and the other node to be reused by the second node and the other node.

Memory reduction for neural networks with fixed structures

A computer-implemented method is provided for hiding overheads on a parallel computing platform. The computer-implemented method includes loading a first kernel overhead and a second kernel overhead in a queue of a second thread, and loading a dummy kernel overhead between the first and second kernel overheads in the queue of second thread. The computer-implemented method further includes loading a waiting process in the queue of a first thread, the waiting process remaining active until a previous kernel of the first and second kernel overheads ends. The computer-implemented method furthers include allocating memory copy overheads related to the previous kernel in the queue of the first thread and allocating a stop process in the queue of the first thread, the stop process configured to stop a dummy kernel, the dummy kernel related to the dummy kernel overhead.

Parallelization and synchronization of procedures to enable overhead hiding

A computer-implemented method for offloading a problem having 2size from processing circuitry to one or more accelerators is disclosed. The processing circuitry and the one or more accelerators include respective memories. In the method, a problem having 2size is divided into a plurality of units each having 2size. At least a part of the units is allocated to the one or more accelerators. A determination is made as to whether there is a remaining part of the units to be allocated onto the processing circuitry. A temporary buffer is prepared on each memory of at least the one or more accelerators. The temporary buffer is used for storing a copy of a dependent unit stored on a different memory, during inter-unit calculation.

Memory offloading a problem using accelerators

Multiple precision integer multiple by matrix-matrix multiplications using 16-bit floating point multiplier

A computer-implemented method is provided for estimating the performance of a GPU application on a new computing machine having an increased GPU-link performance ratio relative to a current computing machine having a current GPU-link performance ratio. The method includes adding a delay to CPU-GPU communication on the current computing machine to simulate a delayed-communication environment on the current computing machine. The method further includes executing the target GPU application in the delayed-communication environment. The method also includes measuring the performance of the target GPU application in the delayed-communication environment. The method additionally includes estimating the performance of the new computing machine having the increased higher GPU-link performance ratio, based on the measured performance of the target GPU application in the delayed-communication environment.

Estimating performance of GPU application for different GPU-link performance ratio

A method for calculating lattice quantum chromodynamics (QCD) that includes loading an aligned spinor and gauge matrix, and constructing a half-spinor for plus and minus from the aligned spinors. In a following step, the method may include calculating a half spinor minus to be transferred to a positive neighbor of the gauge matrix by multiplying the gauge matrix and half-spinor for minus. The half-spinor for plus (Hp) and the half spinor minus may be stored in a shared memory. In a following step, the method may continue with calculating a half spinor plus to be transferred to a negative neighbor of the gauge matrix by multiplying the gauge matrix and the half-spinor for plus. Thereafter, the sum of half-spinors may be calculated.

Innermost data sharing method of lattice quantum chromodynamics calculation

Optimally scheduling a plurality of computation processes including all-to-all communications (A2A) among a plurality of nodes (processors) constituting an n-dimensional (a torus or a mesh) network. The plurality of nodes (processors) constituting the network are divided into a communication (computation process) phase (A2A-L) required for all-to-all communications only among a plurality of nodes included in a first subgroup and a communication (computation process) phase (A2A-P) required for all-to-all communications only among a plurality of nodes included in a second subgroup to perform parallel processing with the phases overlapped with each other across a plurality of threads (thread, thread, thread, and thread). It is also possible to perform the parallel processing with respect to a plurality of computation processes such as a fast Fourier transform (FFT) and a transpose (T) (internal transpose).

Scheduling computation processes including all-to-all communications (A2A) for pipelined parallel processing among plurality of processor nodes constituting network of n-dimensional space

A method for supporting communication among avatars representing users in a virtual world shared by a plurality of users' client terminals and a server connected with each other through a network. The method includes the steps of: accumulating statistical information, which includes (i) a combination of a component of a message transmitted by one or more avatars and avatar motion matching the component, and (ii) a degree of usage of the combination; generating a keyword group from the components of a message transmitted by the one or more avatars in response to the transmission of the message; searching through the statistical information; obtaining one or more avatar motion candidates; and presenting the candidates to the user of the avatar. A system for supporting communication among avatars and a communication support server device in a virtual world are also provided.

Communication support method, system, and server device

An operational object controlling device including a motion detection unit, a motion obtaining unit, a motion feature quantities extraction unit, a template storage unit, an operational object motion storage unit, a motion feature quantities transform unit and an operational object motion obtaining unit. The motion obtaining unit obtains the user's motion detected by the motion detecting unit. The motion feature quantities extraction unit extracts the user's motion feature quantities from the obtained motion. The transform unit transforms the motion feature quantities by using a template obtained from the template storage unit. The motion feature quantities of the operational object are obtained from each of the temporal motion sequences of the operational object in the operational object motion storage unit. The operational object motion obtaining unit obtains one of the temporal motion sequences from the storage unit having the feature quantities close to the user's motion feature quantities.

Operational object controlling device, system, method and program

Enables efficient correction of topological consistency of an input three-dimensional shape approximated in a spatial graph. Structured mesh generation systems of the present invention include: a topology determination apparatus for reading shape data from a shape data storage device to determine topological consistency and outputting data for solving a problem about topological consistency; a decomposable shape generation apparatus for reading the data outputted by the topology determination apparatus, changing a constraint condition of an integer programming problem solver to execute a shape correction process and outputting corrected shape data; and a structured mesh generation apparatus for reading the corrected shape data to generate a structured mesh.

Growing community of inventors

Yokohama, Japan

Jun Doi